Commit 5460da50 authored by Alex Bennée's avatar Alex Bennée Committed by Peter Maydell
Browse files

target-arm/translate-a64: fix gen_load_exclusive 



While testing rth's latest TCG patches with risu I found ldaxp was
broken. Investigating further I found it was broken by 1dd089d0 when
the cmpxchg atomic work was merged. As part of that change the code
attempted to be clever by doing a single 64 bit load and then shuffle
the data around to set the two 32 bit registers.

As I couldn't quite follow the endian magic I've simply partially
reverted the change to the original code gen_load_exclusive code. This
doesn't affect the cmpxchg functionality as that is all done on in
gen_store_exclusive part which is untouched.

I've also restored the comment that was removed (with a slight tweak
to mention cmpxchg).

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Acked-by: default avatarRichard Henderson <rth@twiddle.net>
Message-id: 20161202173454.19179-1-alex.bennee@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent bc66cedb

target-arm/translate-a64.c

+19 −23
Original line number Diff line number Diff line
@@ -1839,41 +1839,37 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) 
    }

}



/*

 * Load/Store exclusive instructions are implemented by remembering

 * the value/address loaded, and seeing if these are the same

 * when the store is performed. This is not actually the architecturally

 * mandated semantics, but it works for typical guest code sequences

 * and avoids having to monitor regular stores.

 *

 * The store exclusive uses the atomic cmpxchg primitives to avoid

 * races in multi-threaded linux-user and when MTTCG softmmu is

 * enabled.

 */

static void gen_load_exclusive(DisasContext *s, int rt, int rt2,

                               TCGv_i64 addr, int size, bool is_pair)

{

    TCGv_i64 tmp = tcg_temp_new_i64();

    TCGMemOp be = s->be_data;

    TCGMemOp memop = s->be_data + size;



    g_assert(size <= 3);

    if (is_pair) {

        TCGv_i64 hitmp = tcg_temp_new_i64();

    tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);



        if (size == 3) {

    if (is_pair) {

        TCGv_i64 addr2 = tcg_temp_new_i64();

        TCGv_i64 hitmp = tcg_temp_new_i64();



            tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s),

                                MO_64 | MO_ALIGN_16 | be);

            tcg_gen_addi_i64(addr2, addr, 8);

            tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s),

                                MO_64 | MO_ALIGN | be);

        g_assert(size >= 2);

        tcg_gen_addi_i64(addr2, addr, 1 << size);

        tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);

        tcg_temp_free_i64(addr2);

        } else {

            g_assert(size == 2);

            tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s),

                                MO_64 | MO_ALIGN | be);

            if (be == MO_LE) {

                tcg_gen_extr32_i64(tmp, hitmp, tmp);

            } else {

                tcg_gen_extr32_i64(hitmp, tmp, tmp);

            }

        }



        tcg_gen_mov_i64(cpu_exclusive_high, hitmp);

        tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);

        tcg_temp_free_i64(hitmp);

    } else {

        tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), size | MO_ALIGN | be);

    }



    tcg_gen_mov_i64(cpu_exclusive_val, tmp);