Commit 53c76c19 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/aarch64: Handle ctz and clz opcodes 



Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent d0b07481

tcg/aarch64/tcg-target.h

+4 −4
Original line number Diff line number Diff line
@@ -62,8 +62,8 @@ typedef enum { 
#define TCG_TARGET_HAS_eqv_i32          1

#define TCG_TARGET_HAS_nand_i32         0

#define TCG_TARGET_HAS_nor_i32          0

#define TCG_TARGET_HAS_clz_i32          0

#define TCG_TARGET_HAS_ctz_i32          0

#define TCG_TARGET_HAS_clz_i32          1

#define TCG_TARGET_HAS_ctz_i32          1

#define TCG_TARGET_HAS_deposit_i32      1

#define TCG_TARGET_HAS_extract_i32      1

#define TCG_TARGET_HAS_sextract_i32     1
@@ -96,8 +96,8 @@ typedef enum { 
#define TCG_TARGET_HAS_eqv_i64          1

#define TCG_TARGET_HAS_nand_i64         0

#define TCG_TARGET_HAS_nor_i64          0

#define TCG_TARGET_HAS_clz_i64          0

#define TCG_TARGET_HAS_ctz_i64          0

#define TCG_TARGET_HAS_clz_i64          1

#define TCG_TARGET_HAS_ctz_i64          1

#define TCG_TARGET_HAS_deposit_i64      1

#define TCG_TARGET_HAS_extract_i64      1

#define TCG_TARGET_HAS_sextract_i64     1

tcg/aarch64/tcg-target.inc.c

+48 −0
Original line number Diff line number Diff line
@@ -339,8 +339,12 @@ typedef enum { 
    /* Conditional select instructions.  */

    I3506_CSEL      = 0x1a800000,

    I3506_CSINC     = 0x1a800400,

    I3506_CSINV     = 0x5a800000,

    I3506_CSNEG     = 0x5a800400,



    /* Data-processing (1 source) instructions.  */

    I3507_CLZ       = 0x5ac01000,

    I3507_RBIT      = 0x5ac00000,

    I3507_REV16     = 0x5ac00400,

    I3507_REV32     = 0x5ac00800,

    I3507_REV64     = 0x5ac00c00,
@@ -993,6 +997,37 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0) 
    tcg_out32(s, sync[a0 & TCG_MO_ALL]);

}



static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,

                         TCGReg a0, TCGArg b, bool const_b, bool is_ctz)

{

    TCGReg a1 = a0;

    if (is_ctz) {

        a1 = TCG_REG_TMP;

        tcg_out_insn(s, 3507, RBIT, ext, a1, a0);

    }

    if (const_b && b == (ext ? 64 : 32)) {

        tcg_out_insn(s, 3507, CLZ, ext, d, a1);

    } else {

        AArch64Insn sel = I3506_CSEL;



        tcg_out_cmp(s, ext, a0, 0, 1);

        tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1);



        if (const_b) {

            if (b == -1) {

                b = TCG_REG_XZR;

                sel = I3506_CSINV;

            } else if (b == 0) {

                b = TCG_REG_XZR;

            } else {

                tcg_out_movi(s, ext, d, b);

                b = d;

            }

        }

        tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE);

    }

}



#ifdef CONFIG_SOFTMMU

/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,

 *                                     TCGMemOpIdx oi, uintptr_t ra)
@@ -1559,6 +1594,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        }

        break;



    case INDEX_op_clz_i64:

    case INDEX_op_clz_i32:

        tcg_out_cltz(s, ext, a0, a1, a2, c2, false);

        break;

    case INDEX_op_ctz_i64:

    case INDEX_op_ctz_i32:

        tcg_out_cltz(s, ext, a0, a1, a2, c2, true);

        break;



    case INDEX_op_brcond_i32:

        a1 = (int32_t)a1;

        /* FALLTHRU */
@@ -1750,11 +1794,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = { 
    { INDEX_op_sar_i32, { "r", "r", "ri" } },

    { INDEX_op_rotl_i32, { "r", "r", "ri" } },

    { INDEX_op_rotr_i32, { "r", "r", "ri" } },

    { INDEX_op_clz_i32, { "r", "r", "rAL" } },

    { INDEX_op_ctz_i32, { "r", "r", "rAL" } },

    { INDEX_op_shl_i64, { "r", "r", "ri" } },

    { INDEX_op_shr_i64, { "r", "r", "ri" } },

    { INDEX_op_sar_i64, { "r", "r", "ri" } },

    { INDEX_op_rotl_i64, { "r", "r", "ri" } },

    { INDEX_op_rotr_i64, { "r", "r", "ri" } },

    { INDEX_op_clz_i64, { "r", "r", "rAL" } },

    { INDEX_op_ctz_i64, { "r", "r", "rAL" } },



    { INDEX_op_brcond_i32, { "r", "rA" } },

    { INDEX_op_brcond_i64, { "r", "rA" } },