Loading target-i386/helper.h +2 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,8 @@ DEF_HELPER_2(divq_EAX, void, env, tl) DEF_HELPER_2(idivq_EAX, void, env, tl) #endif DEF_HELPER_FLAGS_2(bndck, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_2(aam, void, env, int) DEF_HELPER_2(aad, void, env, int) DEF_HELPER_1(aaa, void, env) Loading target-i386/mpx_helper.c +8 −0 Original line number Diff line number Diff line Loading @@ -51,3 +51,11 @@ void cpu_sync_bndcs_hflags(CPUX86State *env) env->hflags = hflags; env->hflags2 = hflags2; } void helper_bndck(CPUX86State *env, uint32_t fail) { if (unlikely(fail)) { env->bndcs_regs.sts = 1; raise_exception_ra(env, EXCP05_BOUND, GETPC()); } } target-i386/translate.c +43 −1 Original line number Diff line number Diff line Loading @@ -1989,6 +1989,21 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) (void)gen_lea_modrm_0(env, s, modrm); } /* Used for BNDCL, BNDCU, BNDCN. */ static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm, TCGCond cond, TCGv_i64 bndv) { TCGv ea = gen_lea_modrm_1(gen_lea_modrm_0(env, s, modrm)); tcg_gen_extu_tl_i64(cpu_tmp1_i64, ea); if (!CODE64(s)) { tcg_gen_ext32u_i64(cpu_tmp1_i64, cpu_tmp1_i64); } tcg_gen_setcond_i64(cond, cpu_tmp1_i64, cpu_tmp1_i64, bndv); tcg_gen_extrl_i64_i32(cpu_tmp2_i32, cpu_tmp1_i64); gen_helper_bndck(cpu_env, cpu_tmp2_i32); } /* used for LEA and MOV AX, mem */ static void gen_add_A0_ds_seg(DisasContext *s) { Loading Loading @@ -7445,7 +7460,26 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (s->flags & HF_MPX_EN_MASK) { mod = (modrm >> 6) & 3; reg = ((modrm >> 3) & 7) | rex_r; if (prefixes & PREFIX_DATA) { if (prefixes & PREFIX_REPZ) { /* bndcl */ if (reg >= 4 || (prefixes & PREFIX_LOCK) || s->aflag == MO_16) { goto illegal_op; } gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]); } else if (prefixes & PREFIX_REPNZ) { /* bndcu */ if (reg >= 4 || (prefixes & PREFIX_LOCK) || s->aflag == MO_16) { goto illegal_op; } TCGv_i64 notu = tcg_temp_new_i64(); tcg_gen_not_i64(notu, cpu_bndu[reg]); gen_bndck(env, s, modrm, TCG_COND_GTU, notu); tcg_temp_free_i64(notu); } else if (prefixes & PREFIX_DATA) { /* bndmov -- from reg/mem */ if (reg >= 4 || s->aflag == MO_16) { goto illegal_op; Loading Loading @@ -7514,6 +7548,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* bnd registers are now in-use */ gen_set_hflag(s, HF_MPX_IU_MASK); break; } else if (prefixes & PREFIX_REPNZ) { /* bndcn */ if (reg >= 4 || (prefixes & PREFIX_LOCK) || s->aflag == MO_16) { goto illegal_op; } gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]); } else if (prefixes & PREFIX_DATA) { /* bndmov -- to reg/mem */ if (reg >= 4 || s->aflag == MO_16) { Loading Loading
target-i386/helper.h +2 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,8 @@ DEF_HELPER_2(divq_EAX, void, env, tl) DEF_HELPER_2(idivq_EAX, void, env, tl) #endif DEF_HELPER_FLAGS_2(bndck, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_2(aam, void, env, int) DEF_HELPER_2(aad, void, env, int) DEF_HELPER_1(aaa, void, env) Loading
target-i386/mpx_helper.c +8 −0 Original line number Diff line number Diff line Loading @@ -51,3 +51,11 @@ void cpu_sync_bndcs_hflags(CPUX86State *env) env->hflags = hflags; env->hflags2 = hflags2; } void helper_bndck(CPUX86State *env, uint32_t fail) { if (unlikely(fail)) { env->bndcs_regs.sts = 1; raise_exception_ra(env, EXCP05_BOUND, GETPC()); } }
target-i386/translate.c +43 −1 Original line number Diff line number Diff line Loading @@ -1989,6 +1989,21 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) (void)gen_lea_modrm_0(env, s, modrm); } /* Used for BNDCL, BNDCU, BNDCN. */ static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm, TCGCond cond, TCGv_i64 bndv) { TCGv ea = gen_lea_modrm_1(gen_lea_modrm_0(env, s, modrm)); tcg_gen_extu_tl_i64(cpu_tmp1_i64, ea); if (!CODE64(s)) { tcg_gen_ext32u_i64(cpu_tmp1_i64, cpu_tmp1_i64); } tcg_gen_setcond_i64(cond, cpu_tmp1_i64, cpu_tmp1_i64, bndv); tcg_gen_extrl_i64_i32(cpu_tmp2_i32, cpu_tmp1_i64); gen_helper_bndck(cpu_env, cpu_tmp2_i32); } /* used for LEA and MOV AX, mem */ static void gen_add_A0_ds_seg(DisasContext *s) { Loading Loading @@ -7445,7 +7460,26 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (s->flags & HF_MPX_EN_MASK) { mod = (modrm >> 6) & 3; reg = ((modrm >> 3) & 7) | rex_r; if (prefixes & PREFIX_DATA) { if (prefixes & PREFIX_REPZ) { /* bndcl */ if (reg >= 4 || (prefixes & PREFIX_LOCK) || s->aflag == MO_16) { goto illegal_op; } gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]); } else if (prefixes & PREFIX_REPNZ) { /* bndcu */ if (reg >= 4 || (prefixes & PREFIX_LOCK) || s->aflag == MO_16) { goto illegal_op; } TCGv_i64 notu = tcg_temp_new_i64(); tcg_gen_not_i64(notu, cpu_bndu[reg]); gen_bndck(env, s, modrm, TCG_COND_GTU, notu); tcg_temp_free_i64(notu); } else if (prefixes & PREFIX_DATA) { /* bndmov -- from reg/mem */ if (reg >= 4 || s->aflag == MO_16) { goto illegal_op; Loading Loading @@ -7514,6 +7548,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* bnd registers are now in-use */ gen_set_hflag(s, HF_MPX_IU_MASK); break; } else if (prefixes & PREFIX_REPNZ) { /* bndcn */ if (reg >= 4 || (prefixes & PREFIX_LOCK) || s->aflag == MO_16) { goto illegal_op; } gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]); } else if (prefixes & PREFIX_DATA) { /* bndmov -- to reg/mem */ if (reg >= 4 || s->aflag == MO_16) { Loading