Commit 51409b9e authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Add stubs for aa32 decodetree 



Add the infrastructure that will become the new decoder.
No instructions adjusted so far.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-3-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 69be3e13

target/arm/Makefile.objs

+18 −0
Original line number Diff line number Diff line
@@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D 
	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)

	$(call quiet-command,\

	  $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)

	$(call quiet-command,\

	  $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)

	$(call quiet-command,\

	  $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\

	  "GEN", $(TARGET_DIR)$@)



target/arm/translate-sve.o: target/arm/decode-sve.inc.c

target/arm/translate.o: target/arm/decode-vfp.inc.c

target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c

target/arm/translate.o: target/arm/decode-a32.inc.c

target/arm/translate.o: target/arm/decode-a32-uncond.inc.c

target/arm/translate.o: target/arm/decode-t32.inc.c



obj-y += tlb_helper.o debug_helper.o

obj-y += translate.o op_helper.o

target/arm/a32-uncond.decode

0 → 100644
+23 −0
Original line number Diff line number Diff line 
# A32 unconditional instructions

#

#  Copyright (c) 2019 Linaro, Ltd

#

# This library is free software; you can redistribute it and/or

# modify it under the terms of the GNU Lesser General Public

# License as published by the Free Software Foundation; either

# version 2 of the License, or (at your option) any later version.

#

# This library is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

# Lesser General Public License for more details.

#

# You should have received a copy of the GNU Lesser General Public

# License along with this library; if not, see <http://www.gnu.org/licenses/>.



#

# This file is processed by scripts/decodetree.py

#

# All insns that have 0xf in insn[31:28] are decoded here.

# All of those that have a COND field in insn[31:28] are in a32.decode

#

target/arm/a32.decode

0 → 100644
+23 −0
Original line number Diff line number Diff line 
# A32 conditional instructions

#

#  Copyright (c) 2019 Linaro, Ltd

#

# This library is free software; you can redistribute it and/or

# modify it under the terms of the GNU Lesser General Public

# License as published by the Free Software Foundation; either

# version 2 of the License, or (at your option) any later version.

#

# This library is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

# Lesser General Public License for more details.

#

# You should have received a copy of the GNU Lesser General Public

# License along with this library; if not, see <http://www.gnu.org/licenses/>.



#

# This file is processed by scripts/decodetree.py

#

# All of the insn that have a COND field in insn[31:28] are here.

# All insns that have 0xf in insn[31:28] are in a32-uncond.decode.

#

target/arm/t32.decode

0 → 100644
+20 −0
Original line number Diff line number Diff line 
# Thumb2 instructions

#

#  Copyright (c) 2019 Linaro, Ltd

#

# This library is free software; you can redistribute it and/or

# modify it under the terms of the GNU Lesser General Public

# License as published by the Free Software Foundation; either

# version 2 of the License, or (at your option) any later version.

#

# This library is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

# Lesser General Public License for more details.

#

# You should have received a copy of the GNU Lesser General Public

# License along with this library; if not, see <http://www.gnu.org/licenses/>.



#

# This file is processed by scripts/decodetree.py

#

target/arm/translate.c

+30 −1
Original line number Diff line number Diff line
@@ -7683,6 +7683,18 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) 
    arm_gen_test_cc(cond ^ 1, s->condlabel);

}



/*

 * Include the generated decoders.

 */



#include "decode-a32.inc.c"

#include "decode-a32-uncond.inc.c"

#include "decode-t32.inc.c"



/*

 * Legacy decoder.

 */



static void disas_arm_insn(DisasContext *s, unsigned int insn)

{

    unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
@@ -7701,6 +7713,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
        return;

    }

    cond = insn >> 28;



    if (cond == 0xf) {

        /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we

         * choose to UNDEF. In ARMv5 and above the space is used
@@ -7709,6 +7722,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
        ARCH(5);



        /* Unconditional instructions.  */

        if (disas_a32_uncond(s, insn)) {

            return;

        }

        /* fall back to legacy decoder */



        if (((insn >> 25) & 7) == 1) {

            /* NEON Data processing.  */

            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -7923,6 +7941,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
           next instruction */

        arm_skip_unless(s, cond);

    }



    if (disas_a32(s, insn)) {

        return;

    }

    /* fall back to legacy decoder */



    if ((insn & 0x0f900000) == 0x03000000) {

        if ((insn & (1 << 21)) == 0) {

            ARCH(6T2);
@@ -9414,6 +9438,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 
        ARCH(6T2);

    }



    if (disas_t32(s, insn)) {

        return;

    }

    /* fall back to legacy decoder */



    rn = (insn >> 16) & 0xf;

    rs = (insn >> 12) & 0xf;

    rd = (insn >> 8) & 0xf;