Commit 4f50c167 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging 



Speculative store buffer bypass mitigation (CVE-2018-3639)

# gpg: Signature made Mon 21 May 2018 23:00:46 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639)
  i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
  i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 9802316e 403503b1

target/i386/cpu.c

+2 −2
Original line number Diff line number Diff line
@@ -805,7 +805,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "spec-ctrl", NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, "ssbd",

        },

        .cpuid_eax = 7,

        .cpuid_needs_ecx = true, .cpuid_ecx = 0,
@@ -836,7 +836,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            "ibpb", NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, "virt-ssbd", NULL, NULL,

            NULL, NULL, NULL, NULL,

        },

        .cpuid_eax = 0x80000008,

target/i386/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -351,6 +351,7 @@ typedef enum X86Seg { 
#define MSR_IA32_FEATURE_CONTROL        0x0000003a

#define MSR_TSC_ADJUST                  0x0000003b

#define MSR_IA32_SPEC_CTRL              0x48

#define MSR_VIRT_SSBD                   0xc001011f

#define MSR_IA32_TSCDEADLINE            0x6e0



#define FEATURE_CONTROL_LOCKED                    (1<<0)
@@ -685,6 +686,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */

#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */



#define KVM_HINTS_DEDICATED (1U << 0)
@@ -1209,6 +1211,7 @@ typedef struct CPUX86State { 
    uint32_t pkru;



    uint64_t spec_ctrl;

    uint64_t virt_ssbd;



    /* End of state preserved by INIT (dummy marker).  */

    struct {} end_init_save;

target/i386/kvm.c

+14 −2
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ static bool has_msr_hv_frequencies; 
static bool has_msr_hv_reenlightenment;

static bool has_msr_xss;

static bool has_msr_spec_ctrl;

static bool has_msr_virt_ssbd;

static bool has_msr_smi_count;



static uint32_t has_architectural_pmu_version;
@@ -1233,6 +1234,9 @@ static int kvm_get_supported_msrs(KVMState *s) 
                case MSR_IA32_SPEC_CTRL:

                    has_msr_spec_ctrl = true;

                    break;

                case MSR_VIRT_SSBD:

                    has_msr_virt_ssbd = true;

                    break;

                }

            }

        }
@@ -1721,6 +1725,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level) 
    if (has_msr_spec_ctrl) {

        kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);

    }

    if (has_msr_virt_ssbd) {

        kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);

    }



#ifdef TARGET_X86_64

    if (lm_capable_kernel) {

        kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
@@ -2100,8 +2108,9 @@ static int kvm_get_msrs(X86CPU *cpu) 
    if (has_msr_spec_ctrl) {

        kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);

    }





    if (has_msr_virt_ssbd) {

        kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);

    }

    if (!env->tsc_valid) {

        kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);

        env->tsc_valid = !runstate_is_running();
@@ -2481,6 +2490,9 @@ static int kvm_get_msrs(X86CPU *cpu) 
        case MSR_IA32_SPEC_CTRL:

            env->spec_ctrl = msrs[i].data;

            break;

        case MSR_VIRT_SSBD:

            env->virt_ssbd = msrs[i].data;

            break;

        case MSR_IA32_RTIT_CTL:

            env->msr_rtit_ctrl = msrs[i].data;

            break;

target/i386/machine.c

+20 −0
Original line number Diff line number Diff line
@@ -916,6 +916,25 @@ static const VMStateDescription vmstate_msr_intel_pt = { 
    }

};



static bool virt_ssbd_needed(void *opaque)

{

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return env->virt_ssbd != 0;

}



static const VMStateDescription vmstate_msr_virt_ssbd = {

    .name = "cpu/virt_ssbd",

    .version_id = 1,

    .minimum_version_id = 1,

    .needed = virt_ssbd_needed,

    .fields = (VMStateField[]){

        VMSTATE_UINT64(env.virt_ssbd, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



VMStateDescription vmstate_x86_cpu = {

    .name = "cpu",

    .version_id = 12,
@@ -1039,6 +1058,7 @@ VMStateDescription vmstate_x86_cpu = { 
        &vmstate_spec_ctrl,

        &vmstate_mcg_ext_ctl,

        &vmstate_msr_intel_pt,

        &vmstate_msr_virt_ssbd,

        NULL

    }

};