Commit 4f2eff36 authored by Peter Maydell's avatar Peter Maydell
Browse files

hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling 



The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from
NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had
misimplemented this as making the bits RAZ/WI from both
Secure and NonSecure states. Fix this bug by checking
attrs.secure so that Secure code can pend and unpend NMIs.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-3-peter.maydell@linaro.org
parent 5a53e2c1

hw/intc/armv7m_nvic.c

+3 −3
Original line number Diff line number Diff line
@@ -830,8 +830,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 
            }

        }

        /* NMIPENDSET */

        if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&

            s->vectors[ARMV7M_EXCP_NMI].pending) {

        if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))

            && s->vectors[ARMV7M_EXCP_NMI].pending) {

            val |= (1 << 31);

        }

        /* ISRPREEMPT: RES0 when halting debug not implemented */
@@ -1193,7 +1193,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
        break;

    }

    case 0xd04: /* Interrupt Control State (ICSR) */

        if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {

        if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {

            if (value & (1 << 31)) {

                armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);

            } else if (value & (1 << 30) &&