Unverified Commit 4e85ea82 authored by Bin Meng's avatar Bin Meng Committed by Palmer Dabbelt
Browse files

riscv: sifive_uart: Generate TX interrupt 



At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.

Note the TX fifo is still unimplemented.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 6b745d4f

hw/riscv/sifive_uart.c

+3 −1
Original line number Diff line number Diff line
@@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s) 
static void update_irq(SiFiveUARTState *s)

{

    int cond = 0;

    if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) {

    if ((s->ie & SIFIVE_UART_IE_TXWM) ||

        ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) {

        cond = 1;

    }

    if (cond) {
@@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr, 
    switch (addr) {

    case SIFIVE_UART_TXFIFO:

        qemu_chr_fe_write(&s->chr, &ch, 1);

        update_irq(s);

        return;

    case SIFIVE_UART_IE:

        s->ie = val64;