Commit 4e5e1215 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Remove gen_intermediate_code_pc 



It is no longer used, so tidy up everything reached by it.
This includes the gen_opc_* arrays, the search_pc parameter
and the inline gen_intermediate_code_internal functions.

Reviewed-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent fca8a500

include/exec/exec-all.h

+0 −1
Original line number Diff line number Diff line
@@ -73,7 +73,6 @@ typedef struct TranslationBlock TranslationBlock; 
#include "qemu/log.h"



void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);

void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);

void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,

                          target_ulong *data);

target-alpha/translate.c

+4 −37
Original line number Diff line number Diff line
@@ -2858,17 +2858,14 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) 
    return ret;

}



static inline void gen_intermediate_code_internal(AlphaCPU *cpu,

                                                  TranslationBlock *tb,

                                                  bool search_pc)

void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)

{

    AlphaCPU *cpu = alpha_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    CPUAlphaState *env = &cpu->env;

    DisasContext ctx, *ctxp = &ctx;

    target_ulong pc_start;

    target_ulong pc_mask;

    uint32_t insn;

    int j, lj = -1;

    ExitStatus ret;

    int num_insns;

    int max_insns;
@@ -2915,18 +2912,6 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 


    gen_tb_start(tb);

    do {

        if (search_pc) {

            j = tcg_op_buf_count();

            if (lj < j) {

                lj++;

                while (lj < j) {

                    tcg_ctx.gen_opc_instr_start[lj++] = 0;

                }

            }

            tcg_ctx.gen_opc_pc[lj] = ctx.pc;

            tcg_ctx.gen_opc_instr_start[lj] = 1;

            tcg_ctx.gen_opc_icount[lj] = num_insns;

        }

        tcg_gen_insn_start(ctx.pc);

        num_insns++;
@@ -2993,16 +2978,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 


    gen_tb_end(tb, num_insns);



    if (search_pc) {

        j = tcg_op_buf_count();

        lj++;

        while (lj <= j) {

            tcg_ctx.gen_opc_instr_start[lj++] = 0;

        }

    } else {

    tb->size = ctx.pc - pc_start;

    tb->icount = num_insns;

    }



#ifdef DEBUG_DISAS

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
@@ -3013,16 +2990,6 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 
#endif

}



void gen_intermediate_code (CPUAlphaState *env, struct TranslationBlock *tb)

{

    gen_intermediate_code_internal(alpha_env_get_cpu(env), tb, false);

}



void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb)

{

    gen_intermediate_code_internal(alpha_env_get_cpu(env), tb, true);

}



void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,

                          target_ulong *data)

{

target-arm/translate-a64.c

+3 −27
Original line number Diff line number Diff line
@@ -11000,14 +11000,11 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) 
    free_tmp_a64(s);

}



void gen_intermediate_code_internal_a64(ARMCPU *cpu,

                                        TranslationBlock *tb,

                                        bool search_pc)

void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)

{

    CPUState *cs = CPU(cpu);

    CPUARMState *env = &cpu->env;

    DisasContext dc1, *dc = &dc1;

    int j, lj;

    target_ulong pc_start;

    target_ulong next_page_start;

    int num_insns;
@@ -11066,7 +11063,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 
    init_tmp_a64_array(dc);



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    lj = -1;

    num_insns = 0;

    max_insns = tb->cflags & CF_COUNT_MASK;

    if (max_insns == 0) {
@@ -11081,18 +11077,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 
    tcg_clear_temp_count();



    do {

        if (search_pc) {

            j = tcg_op_buf_count();

            if (lj < j) {

                lj++;

                while (lj < j) {

                    tcg_ctx.gen_opc_instr_start[lj++] = 0;

                }

            }

            tcg_ctx.gen_opc_pc[lj] = dc->pc;

            tcg_ctx.gen_opc_instr_start[lj] = 1;

            tcg_ctx.gen_opc_icount[lj] = num_insns;

        }

        tcg_gen_insn_start(dc->pc, 0);

        num_insns++;
@@ -11221,14 +11205,6 @@ done_generating: 
        qemu_log("\n");

    }

#endif

    if (search_pc) {

        j = tcg_op_buf_count();

        lj++;

        while (lj <= j) {

            tcg_ctx.gen_opc_instr_start[lj++] = 0;

        }

    } else {

    tb->size = dc->pc - pc_start;

    tb->icount = num_insns;

}
 
}

target-arm/translate.c

+9 −45
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ 
#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)



#include "translate.h"

static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];



#if defined(CONFIG_USER_ONLY)

#define IS_USER(s) 1
@@ -11168,16 +11167,12 @@ undef: 
}



/* generate intermediate code in gen_opc_buf and gen_opparam_buf for

   basic block 'tb'. If search_pc is TRUE, also generate PC

   information for each intermediate instruction. */

static inline void gen_intermediate_code_internal(ARMCPU *cpu,

                                                  TranslationBlock *tb,

                                                  bool search_pc)

   basic block 'tb'.  */

void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)

{

    ARMCPU *cpu = arm_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    CPUARMState *env = &cpu->env;

    DisasContext dc1, *dc = &dc1;

    int j, lj;

    target_ulong pc_start;

    target_ulong next_page_start;

    int num_insns;
@@ -11189,7 +11184,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
     * the A32/T32 complexity to do with conditional execution/IT blocks/etc.

     */

    if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {

        gen_intermediate_code_internal_a64(cpu, tb, search_pc);

        gen_intermediate_code_a64(cpu, tb);

        return;

    }
@@ -11255,7 +11250,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
    /* FIXME: cpu_M0 can probably be the same as cpu_V0.  */

    cpu_M0 = tcg_temp_new_i64();

    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    lj = -1;

    num_insns = 0;

    max_insns = tb->cflags & CF_COUNT_MASK;

    if (max_insns == 0) {
@@ -11289,10 +11283,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
     * (3) if we leave the TB unexpectedly (eg a data abort on a load)

     * then the CPUARMState will be wrong and we need to reset it.

     * This is handled in the same way as restoration of the

     * PC in these situations: we will be called again with search_pc=1

     * and generate a mapping of the condexec bits for each PC in

     * gen_opc_condexec_bits[]. restore_state_to_opc() then uses

     * this to restore the condexec bits.

     * PC in these situations; we save the value of the condexec bits

     * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()

     * then uses this to restore them after an exception.

     *

     * Note that there are no instructions which can read the condexec

     * bits, and none which can write non-static values to them, so
@@ -11309,18 +11302,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
        store_cpu_field(tmp, condexec_bits);

      }

    do {

        if (search_pc) {

            j = tcg_op_buf_count();

            if (lj < j) {

                lj++;

                while (lj < j)

                    tcg_ctx.gen_opc_instr_start[lj++] = 0;

            }

            tcg_ctx.gen_opc_pc[lj] = dc->pc;

            gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);

            tcg_ctx.gen_opc_instr_start[lj] = 1;

            tcg_ctx.gen_opc_icount[lj] = num_insns;

        }

        tcg_gen_insn_start(dc->pc,

                           (dc->condexec_cond << 4) | (dc->condexec_mask >> 1));

        num_insns++;
@@ -11537,26 +11518,9 @@ done_generating: 
        qemu_log("\n");

    }

#endif

    if (search_pc) {

        j = tcg_op_buf_count();

        lj++;

        while (lj <= j)

            tcg_ctx.gen_opc_instr_start[lj++] = 0;

    } else {

    tb->size = dc->pc - pc_start;

    tb->icount = num_insns;

}

}



void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)

{

    gen_intermediate_code_internal(arm_env_get_cpu(env), tb, false);

}



void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb)

{

    gen_intermediate_code_internal(arm_env_get_cpu(env), tb, true);

}



static const char *cpu_mode_names[16] = {

  "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",

target-arm/translate.h

+2 −6
Original line number Diff line number Diff line
@@ -122,9 +122,7 @@ static inline int default_exception_el(DisasContext *s) 


#ifdef TARGET_AARCH64

void a64_translate_init(void);

void gen_intermediate_code_internal_a64(ARMCPU *cpu,

                                        TranslationBlock *tb,

                                        bool search_pc);

void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);

void gen_a64_set_pc_im(uint64_t val);

void aarch64_cpu_dump_state(CPUState *cs, FILE *f,

                            fprintf_function cpu_fprintf, int flags);
@@ -133,9 +131,7 @@ static inline void a64_translate_init(void) 
{

}



static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,

                                                      TranslationBlock *tb,

                                                      bool search_pc)

static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)

{

}