Commit 4dd6517e authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging 



x86 and machine queue for 5.0 soft freeze

Bug fixes:
* memory encryption: Disable mem merge
  (Dr. David Alan Gilbert)

Features:
* New EPYC CPU definitions (Babu Moger)
* Denventon-v2 CPU model (Tao Xu)
* New 'note' field on versioned CPU models (Tao Xu)

Cleanups:
* x86 CPU topology cleanups (Babu Moger)
* cpu: Use DeviceClass reset instead of a special CPUClass reset
  (Peter Maydell)

# gpg: Signature made Wed 18 Mar 2020 01:16:43 GMT
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-and-machine-pull-request:
  hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
  hw/i386: Update structures to save the number of nodes per package
  hw/i386: Remove unnecessary initialization in x86_cpu_new
  machine: Add SMP Sockets in CpuTopology
  hw/i386: Consolidate topology functions
  hw/i386: Introduce X86CPUTopoInfo to contain topology info
  cpu: Use DeviceClass reset instead of a special CPUClass reset
  machine/memory encryption: Disable mem merge
  hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
  i386: Add 2nd Generation AMD EPYC processors
  i386: Add missing cpu feature bits in EPYC model
  target/i386: Add new property note to versioned CPU models
  target/i386: Add Denverton-v2 (no MPX) CPU model

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents a1ba62a0 3c6712ec

hw/core/cpu.c

+4 −15
Original line number Diff line number Diff line
@@ -239,27 +239,16 @@ void cpu_dump_statistics(CPUState *cpu, int flags) 
    }

}



void cpu_class_set_parent_reset(CPUClass *cc,

                                void (*child_reset)(CPUState *cpu),

                                void (**parent_reset)(CPUState *cpu))

{

    *parent_reset = cc->reset;

    cc->reset = child_reset;

}



void cpu_reset(CPUState *cpu)

{

    CPUClass *klass = CPU_GET_CLASS(cpu);



    if (klass->reset != NULL) {

        (*klass->reset)(cpu);

    }

    device_cold_reset(DEVICE(cpu));



    trace_guest_cpu_reset(cpu);

}



static void cpu_common_reset(CPUState *cpu)

static void cpu_common_reset(DeviceState *dev)

{

    CPUState *cpu = CPU(dev);

    CPUClass *cc = CPU_GET_CLASS(cpu);



    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
@@ -419,7 +408,6 @@ static void cpu_class_init(ObjectClass *klass, void *data) 
    CPUClass *k = CPU_CLASS(klass);



    k->parse_features = cpu_common_parse_features;

    k->reset = cpu_common_reset;

    k->get_arch_id = cpu_common_get_arch_id;

    k->has_work = cpu_common_has_work;

    k->get_paging_enabled = cpu_common_get_paging_enabled;
@@ -440,6 +428,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) 
    set_bit(DEVICE_CATEGORY_CPU, dc->categories);

    dc->realize = cpu_common_realizefn;

    dc->unrealize = cpu_common_unrealizefn;

    dc->reset = cpu_common_reset;

    device_class_set_props(dc, cpu_common_props);

    /*

     * Reason: CPUs still need special care by board code: wiring up

hw/core/machine.c

+9 −0
Original line number Diff line number Diff line
@@ -425,6 +425,14 @@ static void machine_set_memory_encryption(Object *obj, const char *value, 


    g_free(ms->memory_encryption);

    ms->memory_encryption = g_strdup(value);



    /*

     * With memory encryption, the host can't see the real contents of RAM,

     * so there's no point in it trying to merge areas.

     */

    if (value) {

        machine_set_mem_merge(obj, false, errp);

    }

}



static bool machine_get_nvdimm(Object *obj, Error **errp)
@@ -749,6 +757,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts) 
        ms->smp.cpus = cpus;

        ms->smp.cores = cores;

        ms->smp.threads = threads;

        ms->smp.sockets = sockets;

    }



    if (ms->smp.cpus > 1) {

hw/i386/pc.c

+29 −24
Original line number Diff line number Diff line
@@ -781,6 +781,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) 
        ms->smp.cpus = cpus;

        ms->smp.cores = cores;

        ms->smp.threads = threads;

        ms->smp.sockets = sockets;

        x86ms->smp_dies = dies;

    }
@@ -1505,7 +1506,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 
    int idx;

    CPUState *cs;

    CPUArchId *cpu_slot;

    X86CPUTopoInfo topo;

    X86CPUTopoIDs topo_ids;

    X86CPU *cpu = X86_CPU(dev);

    CPUX86State *env = &cpu->env;

    MachineState *ms = MACHINE(hotplug_dev);
@@ -1513,6 +1514,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 
    X86MachineState *x86ms = X86_MACHINE(pcms);

    unsigned int smp_cores = ms->smp.cores;

    unsigned int smp_threads = ms->smp.threads;

    X86CPUTopoInfo topo_info;



    if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {

        error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
@@ -1520,7 +1522,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 
        return;

    }



    init_topo_info(&topo_info, x86ms);



    env->nr_dies = x86ms->smp_dies;

    env->nr_nodes = topo_info.nodes_per_pkg;



    /*

     * If APIC ID is not set,
@@ -1571,24 +1576,22 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 
            return;

        }



        topo.pkg_id = cpu->socket_id;

        topo.die_id = cpu->die_id;

        topo.core_id = cpu->core_id;

        topo.smt_id = cpu->thread_id;

        cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,

                                            smp_threads, &topo);

        topo_ids.pkg_id = cpu->socket_id;

        topo_ids.die_id = cpu->die_id;

        topo_ids.core_id = cpu->core_id;

        topo_ids.smt_id = cpu->thread_id;

        cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);

    }



    cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);

    if (!cpu_slot) {

        MachineState *ms = MACHINE(pcms);



        x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,

                                 smp_cores, smp_threads, &topo);

        x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);

        error_setg(errp,

            "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"

            " APIC ID %" PRIu32 ", valid index range 0:%d",

            topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,

            topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id,

            cpu->apic_id, ms->possible_cpus->len - 1);

        return;

    }
@@ -1605,35 +1608,37 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 
    /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()

     * once -smp refactoring is complete and there will be CPU private

     * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */

    x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,

                             smp_cores, smp_threads, &topo);

    if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {

    x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);

    if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {

        error_setg(errp, "property socket-id: %u doesn't match set apic-id:"

            " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);

            " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,

            topo_ids.pkg_id);

        return;

    }

    cpu->socket_id = topo.pkg_id;

    cpu->socket_id = topo_ids.pkg_id;



    if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {

    if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {

        error_setg(errp, "property die-id: %u doesn't match set apic-id:"

            " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);

            " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);

        return;

    }

    cpu->die_id = topo.die_id;

    cpu->die_id = topo_ids.die_id;



    if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {

    if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {

        error_setg(errp, "property core-id: %u doesn't match set apic-id:"

            " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);

            " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,

            topo_ids.core_id);

        return;

    }

    cpu->core_id = topo.core_id;

    cpu->core_id = topo_ids.core_id;



    if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {

    if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {

        error_setg(errp, "property thread-id: %u doesn't match set apic-id:"

            " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);

            " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,

            topo_ids.smt_id);

        return;

    }

    cpu->thread_id = topo.smt_id;

    cpu->thread_id = topo_ids.smt_id;



    if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&

        !kvm_hv_vpindex_settable()) {

hw/i386/x86.c

+32 −19
Original line number Diff line number Diff line
@@ -57,6 +57,17 @@ 
/* Physical Address of PVH entry point read from kernel ELF NOTE */

static size_t pvh_start_addr;



inline void init_topo_info(X86CPUTopoInfo *topo_info,

                           const X86MachineState *x86ms)

{

    MachineState *ms = MACHINE(x86ms);



    topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;

    topo_info->dies_per_pkg = x86ms->smp_dies;

    topo_info->cores_per_die = ms->smp.cores;

    topo_info->threads_per_core = ms->smp.threads;

}



/*

 * Calculates initial APIC ID for a specific CPU index

 *
@@ -68,13 +79,14 @@ static size_t pvh_start_addr; 
uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,

                                    unsigned int cpu_index)

{

    MachineState *ms = MACHINE(x86ms);

    X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);

    X86CPUTopoInfo topo_info;

    uint32_t correct_id;

    static bool warned;



    correct_id = x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores,

                                         ms->smp.threads, cpu_index);

    init_topo_info(&topo_info, x86ms);



    correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);

    if (x86mc->compat_apic_id_mode) {

        if (cpu_index != correct_id && !warned && !qtest_enabled()) {

            error_report("APIC IDs set in compatibility mode, "
@@ -92,13 +104,9 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 
{

    Object *cpu = NULL;

    Error *local_err = NULL;

    CPUX86State *env = NULL;



    cpu = object_new(MACHINE(x86ms)->cpu_type);



    env = &X86_CPU(cpu)->env;

    env->nr_dies = x86ms->smp_dies;



    object_property_set_uint(cpu, apic_id, "apic-id", &local_err);

    object_property_set_bool(cpu, true, "realized", &local_err);
@@ -143,21 +151,24 @@ x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 


int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)

{

   X86CPUTopoInfo topo;

   X86CPUTopoIDs topo_ids;

   X86MachineState *x86ms = X86_MACHINE(ms);

   X86CPUTopoInfo topo_info;



   init_topo_info(&topo_info, x86ms);



   assert(idx < ms->possible_cpus->len);

   x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,

                            x86ms->smp_dies, ms->smp.cores,

                            ms->smp.threads, &topo);

   return topo.pkg_id % ms->numa_state->num_nodes;

                            &topo_info, &topo_ids);

   return topo_ids.pkg_id % ms->numa_state->num_nodes;

}



const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)

{

    X86MachineState *x86ms = X86_MACHINE(ms);

    int i;

    unsigned int max_cpus = ms->smp.max_cpus;

    X86CPUTopoInfo topo_info;

    int i;



    if (ms->possible_cpus) {

        /*
@@ -171,26 +182,28 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 
    ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +

                                  sizeof(CPUArchId) * max_cpus);

    ms->possible_cpus->len = max_cpus;



    init_topo_info(&topo_info, x86ms);



    for (i = 0; i < ms->possible_cpus->len; i++) {

        X86CPUTopoInfo topo;

        X86CPUTopoIDs topo_ids;



        ms->possible_cpus->cpus[i].type = ms->cpu_type;

        ms->possible_cpus->cpus[i].vcpus_count = 1;

        ms->possible_cpus->cpus[i].arch_id =

            x86_cpu_apic_id_from_index(x86ms, i);

        x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,

                                 x86ms->smp_dies, ms->smp.cores,

                                 ms->smp.threads, &topo);

                                 &topo_info, &topo_ids);

        ms->possible_cpus->cpus[i].props.has_socket_id = true;

        ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;

        ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;

        if (x86ms->smp_dies > 1) {

            ms->possible_cpus->cpus[i].props.has_die_id = true;

            ms->possible_cpus->cpus[i].props.die_id = topo.die_id;

            ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;

        }

        ms->possible_cpus->cpus[i].props.has_core_id = true;

        ms->possible_cpus->cpus[i].props.core_id = topo.core_id;

        ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;

        ms->possible_cpus->cpus[i].props.has_thread_id = true;

        ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;

        ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id;

    }

    return ms->possible_cpus;

}

include/hw/boards.h

+2 −0
Original line number Diff line number Diff line
@@ -236,12 +236,14 @@ typedef struct DeviceMemoryState { 
 * @cpus: the number of present logical processors on the machine

 * @cores: the number of cores in one package

 * @threads: the number of threads in one core

 * @sockets: the number of sockets on the machine

 * @max_cpus: the maximum number of logical processors on the machine

 */

typedef struct CpuTopology {

    unsigned int cpus;

    unsigned int cores;

    unsigned int threads;

    unsigned int sockets;

    unsigned int max_cpus;

} CpuTopology;