Commit 4dbb9ed3 authored by Peter Crosthwaite's avatar Peter Crosthwaite Committed by Edgar E. Iglesias
Browse files

xilinx_axienet: pump events as appropriate 



When the conditions blocking receiving are cleared, check for buffered rx
packets.

Signed-off-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
parent bd4a4733

hw/xilinx_axienet.c

+2 −0
Original line number Diff line number Diff line
@@ -516,6 +516,8 @@ static void enet_write(void *opaque, hwaddr addr, 
            s->rcw[addr & 1] = value;

            if ((addr & 1) && value & RCW1_RST) {

                axienet_rx_reset(s);

            } else {

                qemu_flush_queued_packets(qemu_get_queue(s->nic));

            }

            break;