Loading hw/m48t59.c +0 −7 Original line number Diff line number Diff line Loading @@ -468,13 +468,6 @@ uint32_t m48t59_read (void *opaque, uint32_t addr) return retval; } void m48t59_set_addr (void *opaque, uint32_t addr) { M48t59State *NVRAM = opaque; NVRAM->addr = addr; } void m48t59_toggle_lock (void *opaque, int lock) { M48t59State *NVRAM = opaque; Loading hw/nvram.h +0 −1 Original line number Diff line number Diff line Loading @@ -30,6 +30,5 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, int type); M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, uint32_t io_base, uint16_t size, int type); void m48t59_set_addr (void *opaque, uint32_t addr); #endif /* !NVRAM_H */ Loading
hw/m48t59.c +0 −7 Original line number Diff line number Diff line Loading @@ -468,13 +468,6 @@ uint32_t m48t59_read (void *opaque, uint32_t addr) return retval; } void m48t59_set_addr (void *opaque, uint32_t addr) { M48t59State *NVRAM = opaque; NVRAM->addr = addr; } void m48t59_toggle_lock (void *opaque, int lock) { M48t59State *NVRAM = opaque; Loading
hw/nvram.h +0 −1 Original line number Diff line number Diff line Loading @@ -30,6 +30,5 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, int type); M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, uint32_t io_base, uint16_t size, int type); void m48t59_set_addr (void *opaque, uint32_t addr); #endif /* !NVRAM_H */