Commit 4d2e2a03 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE FP Compare with Zero Group 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180627043328.11531-22-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 3887c038

target/arm/helper-sve.h

+42 −0
Original line number Diff line number Diff line
@@ -767,6 +767,48 @@ DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG, 
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,

                   i64, i64, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,

target/arm/sve.decode

+10 −0
Original line number Diff line number Diff line
@@ -140,6 +140,7 @@ 
# One register operand, with governing predicate, vector element size

@rd_pg_rn       ........ esz:2 ... ... ... pg:3 rn:5 rd:5       &rpr_esz

@rd_pg4_pn      ........ esz:2 ... ... .. pg:4 . rn:4 rd:5      &rpr_esz

@pd_pg_rn       ........ esz:2 ... ... ... pg:3 rn:5 . rd:4     &rpr_esz



# One register operand, with governing predicate, no vector element size

@rd_pg_rn_e0    ........ .. ... ... ... pg:3 rn:5 rd:5          &rpr_esz esz=0
@@ -748,6 +749,15 @@ FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn 
FRECPE          01100101 .. 001 110 001100 ..... .....          @rd_rn

FRSQRTE         01100101 .. 001 111 001100 ..... .....          @rd_rn



### SVE FP Compare with Zero Group



FCMGE_ppz0      01100101 .. 0100 00 001 ... ..... 0 ....        @pd_pg_rn

FCMGT_ppz0      01100101 .. 0100 00 001 ... ..... 1 ....        @pd_pg_rn

FCMLT_ppz0      01100101 .. 0100 01 001 ... ..... 0 ....        @pd_pg_rn

FCMLE_ppz0      01100101 .. 0100 01 001 ... ..... 1 ....        @pd_pg_rn

FCMEQ_ppz0      01100101 .. 0100 10 001 ... ..... 0 ....        @pd_pg_rn

FCMNE_ppz0      01100101 .. 0100 11 001 ... ..... 0 ....        @pd_pg_rn



### SVE FP Accumulating Reduction Group



# SVE floating-point serial reduction (predicated)

target/arm/sve_helper.c

+43 −0
Original line number Diff line number Diff line
@@ -3362,6 +3362,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \ 


#define DO_FCMGE(TYPE, X, Y, ST)  TYPE##_compare(Y, X, ST) <= 0

#define DO_FCMGT(TYPE, X, Y, ST)  TYPE##_compare(Y, X, ST) < 0

#define DO_FCMLE(TYPE, X, Y, ST)  TYPE##_compare(X, Y, ST) <= 0

#define DO_FCMLT(TYPE, X, Y, ST)  TYPE##_compare(X, Y, ST) < 0

#define DO_FCMEQ(TYPE, X, Y, ST)  TYPE##_compare_quiet(X, Y, ST) == 0

#define DO_FCMNE(TYPE, X, Y, ST)  TYPE##_compare_quiet(X, Y, ST) != 0

#define DO_FCMUO(TYPE, X, Y, ST)  \
@@ -3385,6 +3387,47 @@ DO_FPCMP_PPZZ_ALL(sve_facgt, DO_FACGT) 
#undef DO_FPCMP_PPZZ_H

#undef DO_FPCMP_PPZZ



/* One operand floating-point comparison against zero, controlled

 * by a predicate.

 */

#define DO_FPCMP_PPZ0(NAME, TYPE, H, OP)                   \

void HELPER(NAME)(void *vd, void *vn, void *vg,            \

                  void *status, uint32_t desc)             \

{                                                          \

    intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6;       \

    uint64_t *d = vd, *g = vg;                             \

    do {                                                   \

        uint64_t out = 0, pg = g[j];                       \

        do {                                               \

            i -= sizeof(TYPE), out <<= sizeof(TYPE);       \

            if ((pg >> (i & 63)) & 1) {                    \

                TYPE nn = *(TYPE *)(vn + H(i));            \

                out |= OP(TYPE, nn, 0, status);            \

            }                                              \

        } while (i & 63);                                  \

        d[j--] = out;                                      \

    } while (i > 0);                                       \

}



#define DO_FPCMP_PPZ0_H(NAME, OP) \

    DO_FPCMP_PPZ0(NAME##_h, float16, H1_2, OP)

#define DO_FPCMP_PPZ0_S(NAME, OP) \

    DO_FPCMP_PPZ0(NAME##_s, float32, H1_4, OP)

#define DO_FPCMP_PPZ0_D(NAME, OP) \

    DO_FPCMP_PPZ0(NAME##_d, float64,     , OP)



#define DO_FPCMP_PPZ0_ALL(NAME, OP) \

    DO_FPCMP_PPZ0_H(NAME, OP)   \

    DO_FPCMP_PPZ0_S(NAME, OP)   \

    DO_FPCMP_PPZ0_D(NAME, OP)



DO_FPCMP_PPZ0_ALL(sve_fcmge0, DO_FCMGE)

DO_FPCMP_PPZ0_ALL(sve_fcmgt0, DO_FCMGT)

DO_FPCMP_PPZ0_ALL(sve_fcmle0, DO_FCMLE)

DO_FPCMP_PPZ0_ALL(sve_fcmlt0, DO_FCMLT)

DO_FPCMP_PPZ0_ALL(sve_fcmeq0, DO_FCMEQ)

DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)



/*

 * Load contiguous data, protected by a governing predicate.

 */

target/arm/translate-sve.c

+43 −0
Original line number Diff line number Diff line
@@ -3554,6 +3554,49 @@ static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a, uint32_t insn) 
    return true;

}



/*

 *** SVE Floating Point Compare with Zero Group

 */



static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a,

                      gen_helper_gvec_3_ptr *fn)

{

    unsigned vsz = vec_full_reg_size(s);

    TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);



    tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd),

                       vec_full_reg_offset(s, a->rn),

                       pred_full_reg_offset(s, a->pg),

                       status, vsz, vsz, 0, fn);

    tcg_temp_free_ptr(status);

}



#define DO_PPZ(NAME, name) \

static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \

{                                                                 \

    static gen_helper_gvec_3_ptr * const fns[3] = {               \

        gen_helper_sve_##name##_h,                                \

        gen_helper_sve_##name##_s,                                \

        gen_helper_sve_##name##_d,                                \

    };                                                            \

    if (a->esz == 0) {                                            \

        return false;                                             \

    }                                                             \

    if (sve_access_check(s)) {                                    \

        do_ppz_fp(s, a, fns[a->esz - 1]);                         \

    }                                                             \

    return true;                                                  \

}



DO_PPZ(FCMGE_ppz0, fcmge0)

DO_PPZ(FCMGT_ppz0, fcmgt0)

DO_PPZ(FCMLE_ppz0, fcmle0)

DO_PPZ(FCMLT_ppz0, fcmlt0)

DO_PPZ(FCMEQ_ppz0, fcmeq0)

DO_PPZ(FCMNE_ppz0, fcmne0)



#undef DO_PPZ



/*

 *** SVE Floating Point Accumulating Reduction Group

 */