Commit 4cfd7bab authored by Wanpeng Li's avatar Wanpeng Li Committed by Paolo Bonzini
Browse files

i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor 



The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR
IA32_MISC_ENABLE MWAIT bit and as userspace has control of them
both, it is userspace's job to configure both bits to match on
the initial setup.

Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: default avatarWanpeng Li <wanpengli@tencent.com>
Message-Id: <1557813999-9175-1-git-send-email-wanpengli@tencent.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent fdd6d824

target/i386/cpu.c

+3 −0
Original line number Diff line number Diff line
@@ -4730,6 +4730,9 @@ static void x86_cpu_reset(CPUState *s) 


    env->pat = 0x0007040600070406ULL;

    env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;

    if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {

        env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;

    }



    memset(env->dr, 0, sizeof(env->dr));

    env->dr[6] = DR6_FIXED_1;

target/i386/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -387,6 +387,7 @@ typedef enum X86Seg { 
#define MSR_IA32_MISC_ENABLE            0x1a0

/* Indicates good rep/movs microcode on some processors: */

#define MSR_IA32_MISC_ENABLE_DEFAULT    1

#define MSR_IA32_MISC_ENABLE_MWAIT      (1ULL << 18)



#define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))

#define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)