Commit 4c97f5b2 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Convert CLZ 



Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour.
This matches the undocumented choice made by the legacy decoder.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-17-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 4ed95abd

target/arm/a32.decode

+4 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
&s_rrrr          s rd rn rm ra

&rrrr            rd rn rm ra

&rrr             rd rn rm

&rr              rd rm

&r               rm

&msr_reg         rn r mask

&mrs_reg         rd r
@@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm 
%sysm            8:1 16:4



@rm              ---- .... .... .... .... .... .... rm:4      &r

@rdm             ---- .... .... .... rd:4 .... .... rm:4      &rr



MRS_bank         ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000  &mrs_bank %sysm

MSR_bank         ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4  &msr_bank %sysm
@@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg 
BX               .... 0001 0010 1111 1111 1111 0001 ....      @rm

BXJ              .... 0001 0010 1111 1111 1111 0010 ....      @rm

BLX_r            .... 0001 0010 1111 1111 1111 0011 ....      @rm



CLZ              .... 0001 0110 1111 .... 1111 0001 ....      @rdm

target/arm/t32.decode

+5 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
&s_rrrr          !extern s rd rn rm ra

&rrrr            !extern rd rn rm ra

&rrr             !extern rd rn rm

&rr              !extern rd rm

&r               !extern rm

&msr_reg         !extern rn r mask

&mrs_reg         !extern rd r
@@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot 
@rnadm           .... .... .... rn:4 ra:4 rd:4 .... rm:4      &rrrr

@rn0dm           .... .... .... rn:4 .... rd:4 .... rm:4      &rrrr ra=0

@rndm            .... .... .... rn:4 .... rd:4 .... rm:4      &rrr

@rdm             .... .... .... .... .... rd:4 .... rm:4      &rr



{

  MUL            1111 1011 0000 .... 1111 .... 0000 ....      @s0_rn0dm
@@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm 
CRC32CH          1111 1010 1101 .... 1111 .... 1001 ....      @rndm

CRC32CW          1111 1010 1101 .... 1111 .... 1010 ....      @rndm



# Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn.

CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm



# Branches and miscellaneous control



%msr_sysm        4:1 8:4

target/arm/translate.c

+15 −16
Original line number Diff line number Diff line
@@ -8490,6 +8490,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) 
    return true;

}



static bool trans_CLZ(DisasContext *s, arg_CLZ *a)

{

    TCGv_i32 tmp;



    if (!ENABLE_ARCH_5) {

        return false;

    }

    tmp = load_reg(s, a->rm);

    tcg_gen_clzi_i32(tmp, tmp, 32);

    store_reg(s, a->rd, tmp);

    return true;

}



/*

 * Legacy decoder.

 */
@@ -8778,18 +8791,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
            /* MSR/MRS (banked/register) */

            /* All done in decodetree.  Illegal ops already signalled.  */

            g_assert_not_reached();

        case 0x1:

            if (op1 == 3) {

                /* clz */

                ARCH(5);

                rd = (insn >> 12) & 0xf;

                tmp = load_reg(s, rm);

                tcg_gen_clzi_i32(tmp, tmp, 32);

                store_reg(s, rd, tmp);

            } else {

                goto illegal_op;

            }

            break;

        case 0x1: /* bx, clz */

        case 0x2: /* bxj */

        case 0x3: /* blx */

        case 0x4: /* crc32 */
@@ -10236,13 +10238,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 
                case 0x08: /* rev */

                case 0x09: /* rev16 */

                case 0x0b: /* revsh */

                case 0x18: /* clz */

                    break;

                case 0x10: /* sel */

                    if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {

                        goto illegal_op;

                    }

                    break;

                case 0x18: /* clz, in decodetree */

                case 0x20: /* crc32/crc32c, in decodetree */

                case 0x21:

                case 0x22:
@@ -10275,9 +10277,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 
                    tcg_temp_free_i32(tmp3);

                    tcg_temp_free_i32(tmp2);

                    break;

                case 0x18: /* clz */

                    tcg_gen_clzi_i32(tmp, tmp, 32);

                    break;

                default:

                    g_assert_not_reached();

                }