Commit 4b5ef0b5 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Edgar E. Iglesias
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microblaze: Speed up base + index addressing mode 



Speed up reg + reg addressing mode when any of the regs is r0.

Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@petalogix.com>
parent b2565c69

target-microblaze/translate.c

+7 −0
Original line number Diff line number Diff line
@@ -788,6 +788,13 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) 


    /* Treat the fast cases first.  */

    if (!dc->type_b) {

        /* If any of the regs is r0, return a ptr to the other.  */

        if (dc->ra == 0) {

            return &cpu_R[dc->rb];

        } else if (dc->rb == 0) {

            return &cpu_R[dc->ra];

        }



        *t = tcg_temp_new();

        tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);

        return t;