Unverified Commit 4b55bc2b authored by Bin Meng's avatar Bin Meng Committed by Palmer Dabbelt
Browse files

riscv: sifive_u: Update UART base addresses and IRQs 



This updates the UART base address and IRQs to match the hardware.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarJonathan Behrens <fintelia@gmail.com>
Acked-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarChih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 806c64b7

hw/riscv/sifive_u.c

+2 −2
Original line number Diff line number Diff line
@@ -62,8 +62,8 @@ static const struct MemmapEntry { 
    [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },

    [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },

    [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },

    [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },

    [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },

    [SIFIVE_U_UART0] =    { 0x10010000,     0x1000 },

    [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },

    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },

    [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },

};

include/hw/riscv/sifive_u.h

+2 −2
Original line number Diff line number Diff line
@@ -65,8 +65,8 @@ enum { 
};



enum {

    SIFIVE_U_UART0_IRQ = 3,

    SIFIVE_U_UART1_IRQ = 4,

    SIFIVE_U_UART0_IRQ = 4,

    SIFIVE_U_UART1_IRQ = 5,

    SIFIVE_U_GEM_IRQ = 0x35

};