Commit 4b1a3e1e authored by Peter Maydell's avatar Peter Maydell Committed by Richard Henderson
Browse files

accel/tcg: Don't treat invalid TLB entries as needing recheck 



In get_page_addr_code() when we check whether the TLB entry
is marked as TLB_RECHECK, we should not go down that code
path if the TLB entry is not valid at all (ie the TLB_INVALID
bit is set).

Tested-by: default avatarLaurent Vivier <laurent@vivier.eu>
Reported-by: default avatarLaurent Vivier <laurent@vivier.eu>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-Id: <20180629161731.16239-1-peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent e4c967a7

accel/tcg/cputlb.c

+2 −1
Original line number Diff line number Diff line
@@ -963,7 +963,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) 
        }

    }



    if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) {

    if (unlikely((env->tlb_table[mmu_idx][index].addr_code &

                  (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) {

        /*

         * This is a TLB_RECHECK access, where the MMU protection

         * covers a smaller range than a target page, and we must