Loading scripts/kvm/vmxcap +7 −7 Original line number Diff line number Diff line Loading @@ -51,15 +51,15 @@ class Control(object): return (val & 0xffffffff, val >> 32) def show(self): print(self.name) mbz, mb1 = self.read2(self.cap_msr) tmbz, tmb1 = 0, 0 mb1, cb1 = self.read2(self.cap_msr) tmb1, tcb1 = 0, 0 if self.true_cap_msr: tmbz, tmb1 = self.read2(self.true_cap_msr) tmb1, tcb1 = self.read2(self.true_cap_msr) for bit in sorted(self.bits.keys()): zero = not (mbz & (1 << bit)) one = mb1 & (1 << bit) true_zero = not (tmbz & (1 << bit)) true_one = tmb1 & (1 << bit) zero = not (mb1 & (1 << bit)) one = cb1 & (1 << bit) true_zero = not (tmb1 & (1 << bit)) true_one = tcb1 & (1 << bit) s= '?' if (self.true_cap_msr and true_zero and true_one and one and not zero): Loading Loading
scripts/kvm/vmxcap +7 −7 Original line number Diff line number Diff line Loading @@ -51,15 +51,15 @@ class Control(object): return (val & 0xffffffff, val >> 32) def show(self): print(self.name) mbz, mb1 = self.read2(self.cap_msr) tmbz, tmb1 = 0, 0 mb1, cb1 = self.read2(self.cap_msr) tmb1, tcb1 = 0, 0 if self.true_cap_msr: tmbz, tmb1 = self.read2(self.true_cap_msr) tmb1, tcb1 = self.read2(self.true_cap_msr) for bit in sorted(self.bits.keys()): zero = not (mbz & (1 << bit)) one = mb1 & (1 << bit) true_zero = not (tmbz & (1 << bit)) true_one = tmb1 & (1 << bit) zero = not (mb1 & (1 << bit)) one = cb1 & (1 << bit) true_zero = not (tmb1 & (1 << bit)) true_one = tcb1 & (1 << bit) s= '?' if (self.true_cap_msr and true_zero and true_one and one and not zero): Loading