Commit 4960f084 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Peter Maydell
Browse files

aspeed/i2c: introduce a state machine 



The Aspeed I2C controller maintains a state machine in the command
register, which is mostly used for debug.

Let's start adding a few states to handle abnormal STOP
commands. Today, the model uses the busy status of the bus as a
condition to do so but it is not precise enough.

Also remove the ABNORMAL bit for failing TX commands. This is
incorrect with respect to the specs.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-4-git-send-email-clg@kaod.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent d0efdc16

hw/i2c/aspeed_i2c.c

+33 −3
Original line number Diff line number Diff line
@@ -169,6 +169,21 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 
    }

}



static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)

{

    bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);

    bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;

}



static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)

{

    return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;

}



/*

 * The state machine needs some refinement. It is only used to track

 * invalid STOP commands for the moment.

 */

static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)

{

    bus->cmd &= ~0xFFFF;
@@ -176,6 +191,11 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 
    bus->intr_status = 0;



    if (bus->cmd & I2CD_M_START_CMD) {

        uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?

            I2CD_MSTARTR : I2CD_MSTART;



        aspeed_i2c_set_state(bus, state);



        if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),

                               extract32(bus->buf, 0, 1))) {

            bus->intr_status |= I2CD_INTR_TX_NAK;
@@ -191,20 +211,26 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 
        if (!i2c_bus_busy(bus->bus)) {

            return;

        }

        aspeed_i2c_set_state(bus, I2CD_MACTIVE);

    }



    if (bus->cmd & I2CD_M_TX_CMD) {

        aspeed_i2c_set_state(bus, I2CD_MTXD);

        if (i2c_send(bus->bus, bus->buf)) {

            bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);

            bus->intr_status |= (I2CD_INTR_TX_NAK);

            i2c_end_transfer(bus->bus);

        } else {

            bus->intr_status |= I2CD_INTR_TX_ACK;

        }

        bus->cmd &= ~I2CD_M_TX_CMD;

        aspeed_i2c_set_state(bus, I2CD_MACTIVE);

    }



    if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {

        int ret = i2c_recv(bus->bus);

        int ret;



        aspeed_i2c_set_state(bus, I2CD_MRXD);

        ret = i2c_recv(bus->bus);

        if (ret < 0) {

            qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);

            ret = 0xff;
@@ -216,16 +242,20 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 
            i2c_nack(bus->bus);

        }

        bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);

        aspeed_i2c_set_state(bus, I2CD_MACTIVE);

    }



    if (bus->cmd & I2CD_M_STOP_CMD) {

        if (!i2c_bus_busy(bus->bus)) {

        if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {

            qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);

            bus->intr_status |= I2CD_INTR_ABNORMAL;

        } else {

            aspeed_i2c_set_state(bus, I2CD_MSTOP);

            i2c_end_transfer(bus->bus);

            bus->intr_status |= I2CD_INTR_NORMAL_STOP;

        }

        bus->cmd &= ~I2CD_M_STOP_CMD;

        aspeed_i2c_set_state(bus, I2CD_IDLE);

    }

}