Commit 495134b7 authored by Bin Meng's avatar Bin Meng Committed by Alistair Francis
Browse files

hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 



Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.

Signed-off-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent e8905c6c

hw/riscv/sifive_e.c

+6 −4
Original line number Diff line number Diff line
@@ -95,14 +95,16 @@ static void sifive_e_machine_init(MachineState *machine) 
        memmap[SIFIVE_E_DTIM].base, main_mem);



    /* Mask ROM reset vector */

    uint32_t reset_vec[2];

    uint32_t reset_vec[4];



    if (s->revb) {

        reset_vec[0] = 0x200102b7;        /* 0x1000: lui     t0,0x20010 */

        reset_vec[1] = 0x200102b7;  /* 0x1004: lui     t0,0x20010 */

    } else {

        reset_vec[0] = 0x204002b7;        /* 0x1000: lui     t0,0x20400 */

        reset_vec[1] = 0x204002b7;  /* 0x1004: lui     t0,0x20400 */

    }

    reset_vec[1] = 0x00028067;        /* 0x1004: jr      t0 */

    reset_vec[2] = 0x00028067;      /* 0x1008: jr      t0 */



    reset_vec[0] = reset_vec[3] = 0;



    /* copy in the reset vector in little_endian byte order */

    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {

hw/riscv/sifive_u.c

+3 −3
Original line number Diff line number Diff line
@@ -430,18 +430,18 @@ static void sifive_u_machine_init(MachineState *machine) 


    /* reset vector */

    uint32_t reset_vec[8] = {

        0x00000000,

        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */

        0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */

        0x01c28593,                    /*     addi   a1, t0, %pcrel_lo(1b) */

        0xf1402573,                    /*     csrr   a0, mhartid  */

#if defined(TARGET_RISCV32)

        0x0182a283,                    /*     lw     t0, 24(t0) */

#elif defined(TARGET_RISCV64)

        0x0182b283,                    /*     ld     t0, 24(t0) */

        0x0182e283,                    /*     lwu    t0, 24(t0) */

#endif

        0x00028067,                    /*     jr     t0 */

        0x00000000,

        start_addr,                    /* start: .dword */

        0x00000000,

                                       /* dtb: */

    };

target/riscv/cpu.c

+8 −8
Original line number Diff line number Diff line
@@ -134,20 +134,20 @@ static void riscv_base_cpu_init(Object *obj) 
    set_resetvec(env, DEFAULT_RSTVEC);

}



static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj)

static void rvxx_sifive_u_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_resetvec(env, 0x1004);

}



static void rvxx_imacu_nommu_cpu_init(Object *obj)

static void rvxx_sifive_e_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_resetvec(env, 0x1004);

    qdev_prop_set_bit(DEVICE(obj), "mmu", false);

}
@@ -578,13 +578,13 @@ static const TypeInfo riscv_cpu_type_infos[] = { 
#if defined(TARGET_RISCV32)

    DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_sifive_e_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_gcsu_priv1_10_0_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_sifive_u_cpu_init),

#elif defined(TARGET_RISCV64)

    DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_gcsu_priv1_10_0_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_sifive_e_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_sifive_u_cpu_init),

#endif

};