Commit 49093916 authored by Bin Meng's avatar Bin Meng Committed by Alistair Francis
Browse files

hw/riscv: sifive_u: Sort the SoC memmap table entries 



Move the flash and DRAM to the end of the SoC memmap table.

Signed-off-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 17aad9f2

hw/riscv/sifive_u.c

+2 −2
Original line number Diff line number Diff line
@@ -80,10 +80,10 @@ static const struct MemmapEntry { 
    [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },

    [SIFIVE_U_GPIO] =     { 0x10060000,     0x1000 },

    [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },

    [SIFIVE_U_FLASH0] =   { 0x20000000, 0x10000000 },

    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },

    [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },

    [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },

    [SIFIVE_U_FLASH0] =   { 0x20000000, 0x10000000 },

    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },

};



#define OTP_SERIAL          1