Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160617' into staging (482b6184) · Commits · SUMMER2020 / students / proj-2021291

hw/arm/virt-acpi-build.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -523,6 +523,7 @@ build_madt(GArray table_data, BIOSLinker linker, VirtGuestInfo *guest_info)
		gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
		gicd->length = sizeof(*gicd);
		gicd->base_address = memmap[VIRT_GIC_DIST].base;
		gicd->version = guest_info->gic_version;

		for (i = 0; i < guest_info->smp_cpus; i++) {
		AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,

hw/intc/Makefile.objs

+4 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,9 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
		common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
		common-obj-$(CONFIG_ARM_GIC) += arm_gicv2m.o
		common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
		common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
		common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
		common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
		common-obj-$(CONFIG_OPENPIC) += openpic.o

		obj-$(CONFIG_APIC) += apic.o apic_common.o
		@@ -32,3 +35,4 @@ obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
		obj-$(CONFIG_S390_FLIC) += s390_flic.o
		obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o
		obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o
		obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o

hw/intc/arm_gicv3.c

0 → 100644

+400 −0

Original line number	Diff line number	Diff line
		/*
		* ARM Generic Interrupt Controller v3
		*
		* Copyright (c) 2015 Huawei.
		* Copyright (c) 2016 Linaro Limited
		* Written by Shlomo Pongratz, Peter Maydell
		*
		* This code is licensed under the GPL, version 2 or (at your option)
		* any later version.
		*/

		/* This file contains implementation code for an interrupt controller
		* which implements the GICv3 architecture. Specifically this is where
		* the device class itself and the functions for handling interrupts
		* coming in and going out live.
		*/

		#include "qemu/osdep.h"
		#include "qapi/error.h"
		#include "hw/sysbus.h"
		#include "hw/intc/arm_gicv3.h"
		#include "gicv3_internal.h"

		static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
		{
		/* Return true if this IRQ at this priority should take
		* precedence over the current recorded highest priority
		* pending interrupt for this CPU. We also return true if
		* the current recorded highest priority pending interrupt
		* is the same as this one (a property which the calling code
		* relies on).
		*/
		if (prio < cs->hppi.prio) {
		return true;
		}
		/* If multiple pending interrupts have the same priority then it is an
		* IMPDEF choice which of them to signal to the CPU. We choose to
		* signal the one with the lowest interrupt number.
		*/
		if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
		return true;
		}
		return false;
		}

		static uint32_t gicd_int_pending(GICv3State *s, int irq)
		{
		/* Recalculate which distributor interrupts are actually pending
		* in the group of 32 interrupts starting at irq (which should be a multiple
		* of 32), and return a 32-bit integer which has a bit set for each
		* interrupt that is eligible to be signaled to the CPU interface.
		*
		* An interrupt is pending if:
		* + the PENDING latch is set OR it is level triggered and the input is 1
		* + its ENABLE bit is set
		* + the GICD enable bit for its group is set
		* Conveniently we can bulk-calculate this with bitwise operations.
		*/
		uint32_t pend, grpmask;
		uint32_t pending = *gic_bmp_ptr32(s->pending, irq);
		uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq);
		uint32_t level = *gic_bmp_ptr32(s->level, irq);
		uint32_t group = *gic_bmp_ptr32(s->group, irq);
		uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq);
		uint32_t enable = *gic_bmp_ptr32(s->enabled, irq);

		pend = pending \| (~edge_trigger & level);
		pend &= enable;

		if (s->gicd_ctlr & GICD_CTLR_DS) {
		grpmod = 0;
		}

		grpmask = 0;
		if (s->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
		grpmask \|= group;
		}
		if (s->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
		grpmask \|= (~group & grpmod);
		}
		if (s->gicd_ctlr & GICD_CTLR_EN_GRP0) {
		grpmask \|= (~group & ~grpmod);
		}
		pend &= grpmask;

		return pend;
		}

		static uint32_t gicr_int_pending(GICv3CPUState *cs)
		{
		/* Recalculate which redistributor interrupts are actually pending,
		* and return a 32-bit integer which has a bit set for each interrupt
		* that is eligible to be signaled to the CPU interface.
		*
		* An interrupt is pending if:
		* + the PENDING latch is set OR it is level triggered and the input is 1
		* + its ENABLE bit is set
		* + the GICD enable bit for its group is set
		* Conveniently we can bulk-calculate this with bitwise operations.
		*/
		uint32_t pend, grpmask, grpmod;

		pend = cs->gicr_ipendr0 \| (~cs->edge_trigger & cs->level);
		pend &= cs->gicr_ienabler0;

		if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
		grpmod = 0;
		} else {
		grpmod = cs->gicr_igrpmodr0;
		}

		grpmask = 0;
		if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
		grpmask \|= cs->gicr_igroupr0;
		}
		if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
		grpmask \|= (~cs->gicr_igroupr0 & grpmod);
		}
		if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP0) {
		grpmask \|= (~cs->gicr_igroupr0 & ~grpmod);
		}
		pend &= grpmask;

		return pend;
		}

		/* Update the interrupt status after state in a redistributor
		* or CPU interface has changed, but don't tell the CPU i/f.
		*/
		static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
		{
		/* Find the highest priority pending interrupt among the
		* redistributor interrupts (SGIs and PPIs).
		*/
		bool seenbetter = false;
		uint8_t prio;
		int i;
		uint32_t pend;

		/* Find out which redistributor interrupts are eligible to be
		* signaled to the CPU interface.
		*/
		pend = gicr_int_pending(cs);

		if (pend) {
		for (i = 0; i < GIC_INTERNAL; i++) {
		if (!(pend & (1 << i))) {
		continue;
		}
		prio = cs->gicr_ipriorityr[i];
		if (irqbetter(cs, i, prio)) {
		cs->hppi.irq = i;
		cs->hppi.prio = prio;
		seenbetter = true;
		}
		}
		}

		if (seenbetter) {
		cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
		}

		/* If the best interrupt we just found would preempt whatever
		* was the previous best interrupt before this update, then
		* we know it's definitely the best one now.
		* If we didn't find an interrupt that would preempt the previous
		* best, and the previous best is outside our range (or there was no
		* previous pending interrupt at all), then that is still valid, and
		* we leave it as the best.
		* Otherwise, we need to do a full update (because the previous best
		* interrupt has reduced in priority and any other interrupt could
		* now be the new best one).
		*/
		if (!seenbetter && cs->hppi.prio != 0xff && cs->hppi.irq < GIC_INTERNAL) {
		gicv3_full_update_noirqset(cs->gic);
		}
		}

		/* Update the GIC status after state in a redistributor or
		* CPU interface has changed, and inform the CPU i/f of
		* its new highest priority pending interrupt.
		*/
		void gicv3_redist_update(GICv3CPUState *cs)
		{
		gicv3_redist_update_noirqset(cs);
		gicv3_cpuif_update(cs);
		}

		/* Update the GIC status after state in the distributor has
		* changed affecting @len interrupts starting at @start,
		* but don't tell the CPU i/f.
		*/
		static void gicv3_update_noirqset(GICv3State *s, int start, int len)
		{
		int i;
		uint8_t prio;
		uint32_t pend = 0;

		assert(start >= GIC_INTERNAL);
		assert(len > 0);

		for (i = 0; i < s->num_cpu; i++) {
		s->cpu[i].seenbetter = false;
		}

		/* Find the highest priority pending interrupt in this range. */
		for (i = start; i < start + len; i++) {
		GICv3CPUState *cs;

		if (i == start \|\| (i & 0x1f) == 0) {
		/* Calculate the next 32 bits worth of pending status */
		pend = gicd_int_pending(s, i & ~0x1f);
		}

		if (!(pend & (1 << (i & 0x1f)))) {
		continue;
		}
		cs = s->gicd_irouter_target[i];
		if (!cs) {
		/* Interrupts targeting no implemented CPU should remain pending
		* and not be forwarded to any CPU.
		*/
		continue;
		}
		prio = s->gicd_ipriority[i];
		if (irqbetter(cs, i, prio)) {
		cs->hppi.irq = i;
		cs->hppi.prio = prio;
		cs->seenbetter = true;
		}
		}

		/* If the best interrupt we just found would preempt whatever
		* was the previous best interrupt before this update, then
		* we know it's definitely the best one now.
		* If we didn't find an interrupt that would preempt the previous
		* best, and the previous best is outside our range (or there was
		* no previous pending interrupt at all), then that
		* is still valid, and we leave it as the best.
		* Otherwise, we need to do a full update (because the previous best
		* interrupt has reduced in priority and any other interrupt could
		* now be the new best one).
		*/
		for (i = 0; i < s->num_cpu; i++) {
		GICv3CPUState *cs = &s->cpu[i];

		if (cs->seenbetter) {
		cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
		}

		if (!cs->seenbetter && cs->hppi.prio != 0xff &&
		cs->hppi.irq >= start && cs->hppi.irq < start + len) {
		gicv3_full_update_noirqset(s);
		break;
		}
		}
		}

		void gicv3_update(GICv3State *s, int start, int len)
		{
		int i;

		gicv3_update_noirqset(s, start, len);
		for (i = 0; i < s->num_cpu; i++) {
		gicv3_cpuif_update(&s->cpu[i]);
		}
		}

		void gicv3_full_update_noirqset(GICv3State *s)
		{
		/* Completely recalculate the GIC status from scratch, but
		* don't update any outbound IRQ lines.
		*/
		int i;

		for (i = 0; i < s->num_cpu; i++) {
		s->cpu[i].hppi.prio = 0xff;
		}

		/* Note that we can guarantee that these functions will not
		* recursively call back into gicv3_full_update(), because
		* at each point the "previous best" is always outside the
		* range we ask them to update.
		*/
		gicv3_update_noirqset(s, GIC_INTERNAL, s->num_irq - GIC_INTERNAL);

		for (i = 0; i < s->num_cpu; i++) {
		gicv3_redist_update_noirqset(&s->cpu[i]);
		}
		}

		void gicv3_full_update(GICv3State *s)
		{
		/* Completely recalculate the GIC status from scratch, including
		* updating outbound IRQ lines.
		*/
		int i;

		gicv3_full_update_noirqset(s);
		for (i = 0; i < s->num_cpu; i++) {
		gicv3_cpuif_update(&s->cpu[i]);
		}
		}

		/* Process a change in an external IRQ input. */
		static void gicv3_set_irq(void *opaque, int irq, int level)
		{
		/* Meaning of the 'irq' parameter:
		* [0..N-1] : external interrupts
		* [N..N+31] : PPI (internal) interrupts for CPU 0
		* [N+32..N+63] : PPI (internal interrupts for CPU 1
		* ...
		*/
		GICv3State *s = opaque;

		if (irq < (s->num_irq - GIC_INTERNAL)) {
		/* external interrupt (SPI) */
		gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level);
		} else {
		/* per-cpu interrupt (PPI) */
		int cpu;

		irq -= (s->num_irq - GIC_INTERNAL);
		cpu = irq / GIC_INTERNAL;
		irq %= GIC_INTERNAL;
		assert(cpu < s->num_cpu);
		/* Raising SGIs via this function would be a bug in how the board
		* model wires up interrupts.
		*/
		assert(irq >= GIC_NR_SGIS);
		gicv3_redist_set_irq(&s->cpu[cpu], irq, level);
		}
		}

		static void arm_gicv3_post_load(GICv3State *s)
		{
		/* Recalculate our cached idea of the current highest priority
		* pending interrupt, but don't set IRQ or FIQ lines.
		*/
		gicv3_full_update_noirqset(s);
		/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
		gicv3_cache_all_target_cpustates(s);
		}

		static const MemoryRegionOps gic_ops[] = {
		{
		.read_with_attrs = gicv3_dist_read,
		.write_with_attrs = gicv3_dist_write,
		.endianness = DEVICE_NATIVE_ENDIAN,
		},
		{
		.read_with_attrs = gicv3_redist_read,
		.write_with_attrs = gicv3_redist_write,
		.endianness = DEVICE_NATIVE_ENDIAN,
		}
		};

		static void arm_gic_realize(DeviceState dev, Error *errp)
		{
		/* Device instance realize function for the GIC sysbus device */
		GICv3State *s = ARM_GICV3(dev);
		ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s);
		Error *local_err = NULL;

		agc->parent_realize(dev, &local_err);
		if (local_err) {
		error_propagate(errp, local_err);
		return;
		}

		gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);

		gicv3_init_cpuif(s);
		}

		static void arm_gicv3_class_init(ObjectClass klass, void data)
		{
		DeviceClass *dc = DEVICE_CLASS(klass);
		ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
		ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);

		agcc->post_load = arm_gicv3_post_load;
		agc->parent_realize = dc->realize;
		dc->realize = arm_gic_realize;
		}

		static const TypeInfo arm_gicv3_info = {
		.name = TYPE_ARM_GICV3,
		.parent = TYPE_ARM_GICV3_COMMON,
		.instance_size = sizeof(GICv3State),
		.class_init = arm_gicv3_class_init,
		.class_size = sizeof(ARMGICv3Class),
		};

		static void arm_gicv3_register_types(void)
		{
		type_register_static(&arm_gicv3_info);
		}

		type_init(arm_gicv3_register_types)

hw/intc/arm_gicv3_common.c

+217 −8

Original line number	Diff line number	Diff line
		@@ -3,8 +3,9 @@
		*
		* Copyright (c) 2012 Linaro Limited
		* Copyright (c) 2015 Huawei.
		* Copyright (c) 2015 Samsung Electronics Co., Ltd.
		* Written by Peter Maydell
		* Extended to 64 cores by Shlomo Pongratz
		* Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		@@ -22,7 +23,10 @@

		#include "qemu/osdep.h"
		#include "qapi/error.h"
		#include "qom/cpu.h"
		#include "hw/intc/arm_gicv3_common.h"
		#include "gicv3_internal.h"
		#include "hw/arm/linux-boot-if.h"

		static void gicv3_pre_save(void *opaque)
		{
		@@ -45,11 +49,59 @@ static int gicv3_post_load(void *opaque, int version_id)
		return 0;
		}

		static const VMStateDescription vmstate_gicv3_cpu = {
		.name = "arm_gicv3_cpu",
		.version_id = 1,
		.minimum_version_id = 1,
		.fields = (VMStateField[]) {
		VMSTATE_UINT32(level, GICv3CPUState),
		VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
		VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
		VMSTATE_UINT32(gicr_waker, GICv3CPUState),
		VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
		VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
		VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
		VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
		VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
		VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
		VMSTATE_UINT32(edge_trigger, GICv3CPUState),
		VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
		VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
		VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
		VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
		VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
		VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
		VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
		VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
		VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
		VMSTATE_END_OF_LIST()
		}
		};

		static const VMStateDescription vmstate_gicv3 = {
		.name = "arm_gicv3",
		.unmigratable = 1,
		.version_id = 1,
		.minimum_version_id = 1,
		.pre_save = gicv3_pre_save,
		.post_load = gicv3_post_load,
		.fields = (VMStateField[]) {
		VMSTATE_UINT32(gicd_ctlr, GICv3State),
		VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
		VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
		VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
		VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
		VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
		DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
		VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
		vmstate_gicv3_cpu, GICv3CPUState),
		VMSTATE_END_OF_LIST()
		}
		};

		void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
		@@ -68,14 +120,11 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
		i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
		qdev_init_gpio_in(DEVICE(s), handler, i);

		s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq));
		s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq));

		for (i = 0; i < s->num_cpu; i++) {
		sysbus_init_irq(sbd, &s->parent_irq[i]);
		sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
		}
		for (i = 0; i < s->num_cpu; i++) {
		sysbus_init_irq(sbd, &s->parent_fiq[i]);
		sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
		}

		memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
		@@ -90,6 +139,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
		static void arm_gicv3_common_realize(DeviceState dev, Error *errp)
		{
		GICv3State *s = ARM_GICV3_COMMON(dev);
		int i;

		/* revision property is actually reserved and currently used only in order
		* to keep the interface compatible with GICv2 code, avoiding extra
		@@ -100,11 +150,164 @@ static void arm_gicv3_common_realize(DeviceState dev, Error *errp)
		error_setg(errp, "unsupported GIC revision %d", s->revision);
		return;
		}

		if (s->num_irq > GICV3_MAXIRQ) {
		error_setg(errp,
		"requested %u interrupt lines exceeds GIC maximum %d",
		s->num_irq, GICV3_MAXIRQ);
		return;
		}
		if (s->num_irq < GIC_INTERNAL) {
		error_setg(errp,
		"requested %u interrupt lines is below GIC minimum %d",
		s->num_irq, GIC_INTERNAL);
		return;
		}

		/* ITLinesNumber is represented as (N / 32) - 1, so this is an
		* implementation imposed restriction, not an architectural one,
		* so we don't have to deal with bitfields where only some of the
		* bits in a 32-bit word should be valid.
		*/
		if (s->num_irq % 32) {
		error_setg(errp,
		"%d interrupt lines unsupported: not divisible by 32",
		s->num_irq);
		return;
		}

		s->cpu = g_new0(GICv3CPUState, s->num_cpu);

		for (i = 0; i < s->num_cpu; i++) {
		CPUState *cpu = qemu_get_cpu(i);
		uint64_t cpu_affid;
		int last;

		s->cpu[i].cpu = cpu;
		s->cpu[i].gic = s;

		/* Pre-construct the GICR_TYPER:
		* For our implementation:
		* Top 32 bits are the affinity value of the associated CPU
		* CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
		* Processor_Number == CPU index starting from 0
		* DPGS == 0 (GICR_CTLR.DPG* not supported)
		* Last == 1 if this is the last redistributor in a series of
		* contiguous redistributor pages
		* DirectLPI == 0 (direct injection of LPIs not supported)
		* VLPIS == 0 (virtual LPIs not supported)
		* PLPIS == 0 (physical LPIs not supported)
		*/
		cpu_affid = object_property_get_int(OBJECT(cpu), "mp-affinity", NULL);
		last = (i == s->num_cpu - 1);

		/* The CPU mp-affinity property is in MPIDR register format; squash
		* the affinity bytes into 32 bits as the GICR_TYPER has them.
		*/
		cpu_affid = (cpu_affid & 0xFF00000000ULL >> 8) \| (cpu_affid & 0xFFFFFF);
		s->cpu[i].gicr_typer = (cpu_affid << 32) \|
		(1 << 24) \|
		(i << 8) \|
		(last << 4);
		}
		}

		static void arm_gicv3_common_reset(DeviceState *dev)
		{
		/* TODO */
		GICv3State *s = ARM_GICV3_COMMON(dev);
		int i;

		for (i = 0; i < s->num_cpu; i++) {
		GICv3CPUState *cs = &s->cpu[i];

		cs->level = 0;
		cs->gicr_ctlr = 0;
		cs->gicr_statusr[GICV3_S] = 0;
		cs->gicr_statusr[GICV3_NS] = 0;
		cs->gicr_waker = GICR_WAKER_ProcessorSleep \| GICR_WAKER_ChildrenAsleep;
		cs->gicr_propbaser = 0;
		cs->gicr_pendbaser = 0;
		/* If we're resetting a TZ-aware GIC as if secure firmware
		* had set it up ready to start a kernel in non-secure, we
		* need to set interrupts to group 1 so the kernel can use them.
		* Otherwise they reset to group 0 like the hardware.
		*/
		if (s->irq_reset_nonsecure) {
		cs->gicr_igroupr0 = 0xffffffff;
		} else {
		cs->gicr_igroupr0 = 0;
		}

		cs->gicr_ienabler0 = 0;
		cs->gicr_ipendr0 = 0;
		cs->gicr_iactiver0 = 0;
		cs->edge_trigger = 0xffff;
		cs->gicr_igrpmodr0 = 0;
		cs->gicr_nsacr = 0;
		memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));

		cs->hppi.prio = 0xff;

		/* State in the CPU interface must not be reset here, because it
		* is part of the CPU's reset domain, not the GIC device's.
		*/
		}

		/* For our implementation affinity routing is always enabled */
		if (s->security_extn) {
		s->gicd_ctlr = GICD_CTLR_ARE_S \| GICD_CTLR_ARE_NS;
		} else {
		s->gicd_ctlr = GICD_CTLR_DS \| GICD_CTLR_ARE;
		}

		s->gicd_statusr[GICV3_S] = 0;
		s->gicd_statusr[GICV3_NS] = 0;

		memset(s->group, 0, sizeof(s->group));
		memset(s->grpmod, 0, sizeof(s->grpmod));
		memset(s->enabled, 0, sizeof(s->enabled));
		memset(s->pending, 0, sizeof(s->pending));
		memset(s->active, 0, sizeof(s->active));
		memset(s->level, 0, sizeof(s->level));
		memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
		memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
		memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
		memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
		/* GICD_IROUTER are UNKNOWN at reset so in theory the guest must
		* write these to get sane behaviour and we need not populate the
		* pointer cache here; however having the cache be different for
		* "happened to be 0 from reset" and "guest wrote 0" would be
		* too confusing.
		*/
		gicv3_cache_all_target_cpustates(s);

		if (s->irq_reset_nonsecure) {
		/* If we're resetting a TZ-aware GIC as if secure firmware
		* had set it up ready to start a kernel in non-secure, we
		* need to set interrupts to group 1 so the kernel can use them.
		* Otherwise they reset to group 0 like the hardware.
		*/
		for (i = GIC_INTERNAL; i < s->num_irq; i++) {
		gicv3_gicd_group_set(s, i);
		}
		}
		}

		static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
		bool secure_boot)
		{
		GICv3State *s = ARM_GICV3_COMMON(obj);

		if (s->security_extn && !secure_boot) {
		/* We're directly booting a kernel into NonSecure. If this GIC
		* implements the security extensions then we must configure it
		* to have all the interrupts be NonSecure (this is a job that
		* is done by the Secure boot firmware in real hardware, and in
		* this mode QEMU is acting as a minimalist firmware-and-bootloader
		* equivalent).
		*/
		s->irq_reset_nonsecure = true;
		}
		}

		static Property arm_gicv3_common_properties[] = {
		@@ -118,11 +321,13 @@ static Property arm_gicv3_common_properties[] = {
		static void arm_gicv3_common_class_init(ObjectClass klass, void data)
		{
		DeviceClass *dc = DEVICE_CLASS(klass);
		ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);

		dc->reset = arm_gicv3_common_reset;
		dc->realize = arm_gicv3_common_realize;
		dc->props = arm_gicv3_common_properties;
		dc->vmsd = &vmstate_gicv3;
		albifc->arm_linux_init = arm_gic_common_linux_init;
		}

		static const TypeInfo arm_gicv3_common_type = {
		@@ -132,6 +337,10 @@ static const TypeInfo arm_gicv3_common_type = {
		.class_size = sizeof(ARMGICv3CommonClass),
		.class_init = arm_gicv3_common_class_init,
		.abstract = true,
		.interfaces = (InterfaceInfo []) {
		{ TYPE_ARM_LINUX_BOOT_IF },
		{ },
		},
		};

		static void register_types(void)

hw/intc/arm_gicv3_cpuif.c

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