Commit 474f3938 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging 



MIPS queue for June 21st, 2019

# gpg: Signature made Fri 21 Jun 2019 10:46:57 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-jun-21-2019:
  target/mips: Fix emulation of ILVR.<B|H|W> on big endian host
  target/mips: Fix emulation of ILVL.<B|H|W> on big endian host
  target/mips: Fix emulation of ILVOD.<B|H|W> on big endian host
  target/mips: Fix emulation of ILVEV.<B|H|W> on big endian host
  tests/tcg: target/mips: Amend tests for MSA pack instructions
  tests/tcg: target/mips: Include isa/ase and group name in test output
  target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c
  target/mips: Fix some space checkpatch errors in translate.c
  MAINTAINERS: Consolidate MIPS disassembler-related items
  MAINTAINERS: Update file items for MIPS Malta board

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 68d7ff0c 14f5d874

MAINTAINERS

+2 −4
Original line number Diff line number Diff line
@@ -212,9 +212,7 @@ R: Aleksandar Rikalo <arikalo@wavecomp.com> 
S: Maintained

F: target/mips/

F: default-configs/*mips*

F: disas/mips.c

F: disas/nanomips.cpp

F: disas/nanomips.h

F: disas/*mips*

F: hw/intc/mips_gic.c

F: hw/mips/

F: hw/misc/mips_*
@@ -930,6 +928,7 @@ M: Aurelien Jarno <aurelien@aurel32.net> 
R: Aleksandar Rikalo <arikalo@wavecomp.com>

S: Maintained

F: hw/mips/mips_malta.c

F: hw/mips/gt64xxx_pci.c

F: tests/acceptance/linux_ssh_mips_malta.py



Mipssim
@@ -2325,7 +2324,6 @@ M: Aurelien Jarno <aurelien@aurel32.net> 
R: Aleksandar Rikalo <arikalo@wavecomp.com>

S: Maintained

F: tcg/mips/

F: disas/mips.c



PPC TCG target

M: Richard Henderson <rth@twiddle.net>

target/mips/msa_helper.c

+148 −0
Original line number Diff line number Diff line
@@ -1737,6 +1737,24 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->b[8]  = pws->b[9];

        pwd->b[9]  = pwt->b[9];

        pwd->b[10] = pws->b[11];

        pwd->b[11] = pwt->b[11];

        pwd->b[12] = pws->b[13];

        pwd->b[13] = pwt->b[13];

        pwd->b[14] = pws->b[15];

        pwd->b[15] = pwt->b[15];

        pwd->b[0]  = pws->b[1];

        pwd->b[1]  = pwt->b[1];

        pwd->b[2]  = pws->b[3];

        pwd->b[3]  = pwt->b[3];

        pwd->b[4]  = pws->b[5];

        pwd->b[5]  = pwt->b[5];

        pwd->b[6]  = pws->b[7];

        pwd->b[7]  = pwt->b[7];

#else

        pwd->b[15] = pws->b[14];

        pwd->b[14] = pwt->b[14];

        pwd->b[13] = pws->b[12];
@@ -1753,8 +1771,19 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->b[2]  = pwt->b[2];

        pwd->b[1]  = pws->b[0];

        pwd->b[0]  = pwt->b[0];

#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->h[4] = pws->h[5];

        pwd->h[5] = pwt->h[5];

        pwd->h[6] = pws->h[7];

        pwd->h[7] = pwt->h[7];

        pwd->h[0] = pws->h[1];

        pwd->h[1] = pwt->h[1];

        pwd->h[2] = pws->h[3];

        pwd->h[3] = pwt->h[3];

#else

        pwd->h[7] = pws->h[6];

        pwd->h[6] = pwt->h[6];

        pwd->h[5] = pws->h[4];
@@ -1763,12 +1792,20 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->h[2] = pwt->h[2];

        pwd->h[1] = pws->h[0];

        pwd->h[0] = pwt->h[0];

#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->w[2] = pws->w[3];

        pwd->w[3] = pwt->w[3];

        pwd->w[0] = pws->w[1];

        pwd->w[1] = pwt->w[1];

#else

        pwd->w[3] = pws->w[2];

        pwd->w[2] = pwt->w[2];

        pwd->w[1] = pws->w[0];

        pwd->w[0] = pwt->w[0];

#endif

        break;

    case DF_DOUBLE:

        pwd->d[1] = pws->d[0];
@@ -1788,6 +1825,24 @@ void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->b[7]  = pwt->b[6];

        pwd->b[6]  = pws->b[6];

        pwd->b[5]  = pwt->b[4];

        pwd->b[4]  = pws->b[4];

        pwd->b[3]  = pwt->b[2];

        pwd->b[2]  = pws->b[2];

        pwd->b[1]  = pwt->b[0];

        pwd->b[0]  = pws->b[0];

        pwd->b[15] = pwt->b[14];

        pwd->b[14] = pws->b[14];

        pwd->b[13] = pwt->b[12];

        pwd->b[12] = pws->b[12];

        pwd->b[11] = pwt->b[10];

        pwd->b[10] = pws->b[10];

        pwd->b[9]  = pwt->b[8];

        pwd->b[8]  = pws->b[8];

#else

        pwd->b[0]  = pwt->b[1];

        pwd->b[1]  = pws->b[1];

        pwd->b[2]  = pwt->b[3];
@@ -1804,8 +1859,19 @@ void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->b[13] = pws->b[13];

        pwd->b[14] = pwt->b[15];

        pwd->b[15] = pws->b[15];

#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->h[3] = pwt->h[2];

        pwd->h[2] = pws->h[2];

        pwd->h[1] = pwt->h[0];

        pwd->h[0] = pws->h[0];

        pwd->h[7] = pwt->h[6];

        pwd->h[6] = pws->h[6];

        pwd->h[5] = pwt->h[4];

        pwd->h[4] = pws->h[4];

#else

        pwd->h[0] = pwt->h[1];

        pwd->h[1] = pws->h[1];

        pwd->h[2] = pwt->h[3];
@@ -1814,12 +1880,20 @@ void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->h[5] = pws->h[5];

        pwd->h[6] = pwt->h[7];

        pwd->h[7] = pws->h[7];

#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->w[1] = pwt->w[0];

        pwd->w[0] = pws->w[0];

        pwd->w[3] = pwt->w[2];

        pwd->w[2] = pws->w[2];

#else

        pwd->w[0] = pwt->w[1];

        pwd->w[1] = pws->w[1];

        pwd->w[2] = pwt->w[3];

        pwd->w[3] = pws->w[3];

#endif

        break;

    case DF_DOUBLE:

        pwd->d[0] = pwt->d[1];
@@ -1839,6 +1913,24 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->b[7]  = pwt->b[15];

        pwd->b[6]  = pws->b[15];

        pwd->b[5]  = pwt->b[14];

        pwd->b[4]  = pws->b[14];

        pwd->b[3]  = pwt->b[13];

        pwd->b[2]  = pws->b[13];

        pwd->b[1]  = pwt->b[12];

        pwd->b[0]  = pws->b[12];

        pwd->b[15] = pwt->b[11];

        pwd->b[14] = pws->b[11];

        pwd->b[13] = pwt->b[10];

        pwd->b[12] = pws->b[10];

        pwd->b[11] = pwt->b[9];

        pwd->b[10] = pws->b[9];

        pwd->b[9]  = pwt->b[8];

        pwd->b[8]  = pws->b[8];

#else

        pwd->b[0]  = pwt->b[8];

        pwd->b[1]  = pws->b[8];

        pwd->b[2]  = pwt->b[9];
@@ -1855,8 +1947,19 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->b[13] = pws->b[14];

        pwd->b[14] = pwt->b[15];

        pwd->b[15] = pws->b[15];

#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->h[3] = pwt->h[7];

        pwd->h[2] = pws->h[7];

        pwd->h[1] = pwt->h[6];

        pwd->h[0] = pws->h[6];

        pwd->h[7] = pwt->h[5];

        pwd->h[6] = pws->h[5];

        pwd->h[5] = pwt->h[4];

        pwd->h[4] = pws->h[4];

#else

        pwd->h[0] = pwt->h[4];

        pwd->h[1] = pws->h[4];

        pwd->h[2] = pwt->h[5];
@@ -1865,12 +1968,20 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->h[5] = pws->h[6];

        pwd->h[6] = pwt->h[7];

        pwd->h[7] = pws->h[7];

#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->w[1] = pwt->w[3];

        pwd->w[0] = pws->w[3];

        pwd->w[3] = pwt->w[2];

        pwd->w[2] = pws->w[2];

#else

        pwd->w[0] = pwt->w[2];

        pwd->w[1] = pws->w[2];

        pwd->w[2] = pwt->w[3];

        pwd->w[3] = pws->w[3];

#endif

        break;

    case DF_DOUBLE:

        pwd->d[0] = pwt->d[1];
@@ -1890,6 +2001,24 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->b[8]  = pws->b[0];

        pwd->b[9]  = pwt->b[0];

        pwd->b[10] = pws->b[1];

        pwd->b[11] = pwt->b[1];

        pwd->b[12] = pws->b[2];

        pwd->b[13] = pwt->b[2];

        pwd->b[14] = pws->b[3];

        pwd->b[15] = pwt->b[3];

        pwd->b[0]  = pws->b[4];

        pwd->b[1]  = pwt->b[4];

        pwd->b[2]  = pws->b[5];

        pwd->b[3]  = pwt->b[5];

        pwd->b[4]  = pws->b[6];

        pwd->b[5]  = pwt->b[6];

        pwd->b[6]  = pws->b[7];

        pwd->b[7]  = pwt->b[7];

#else

        pwd->b[15] = pws->b[7];

        pwd->b[14] = pwt->b[7];

        pwd->b[13] = pws->b[6];
@@ -1906,8 +2035,19 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->b[2]  = pwt->b[1];

        pwd->b[1]  = pws->b[0];

        pwd->b[0]  = pwt->b[0];

#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->h[4] = pws->h[0];

        pwd->h[5] = pwt->h[0];

        pwd->h[6] = pws->h[1];

        pwd->h[7] = pwt->h[1];

        pwd->h[0] = pws->h[2];

        pwd->h[1] = pwt->h[2];

        pwd->h[2] = pws->h[3];

        pwd->h[3] = pwt->h[3];

#else

        pwd->h[7] = pws->h[3];

        pwd->h[6] = pwt->h[3];

        pwd->h[5] = pws->h[2];
@@ -1916,12 +2056,20 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
        pwd->h[2] = pwt->h[1];

        pwd->h[1] = pws->h[0];

        pwd->h[0] = pwt->h[0];

#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

        pwd->w[2] = pws->w[0];

        pwd->w[3] = pwt->w[0];

        pwd->w[0] = pws->w[1];

        pwd->w[1] = pwt->w[1];

#else

        pwd->w[3] = pws->w[1];

        pwd->w[2] = pwt->w[1];

        pwd->w[1] = pws->w[0];

        pwd->w[0] = pwt->w[0];

#endif

        break;

    case DF_DOUBLE:

        pwd->d[1] = pws->d[0];

target/mips/translate.c

+255 −190
Original line number Diff line number Diff line
@@ -2619,26 +2619,28 @@ static const char * const mxuregnames[] = { 
/* General purpose registers moves. */

static inline void gen_load_gpr(TCGv t, int reg)

{

    if (reg == 0)

    if (reg == 0) {

        tcg_gen_movi_tl(t, 0);

    else

    } else {

        tcg_gen_mov_tl(t, cpu_gpr[reg]);

    }

}









static inline void gen_store_gpr(TCGv t, int reg)









{









    if (reg != 0)









    if (reg != 0) {









        tcg_gen_mov_tl(cpu_gpr[reg], t);









    }









}

















/* Moves to/from shadow registers. */









static inline void gen_load_srsgpr(int from, int to)









{









    TCGv t0 = tcg_temp_new();

















    if (from == 0)









    if (from == 0) {









        tcg_gen_movi_tl(t0, 0);









    else {









    } else {









        TCGv_i32 t2 = tcg_temp_new_i32();









        TCGv_ptr addr = tcg_temp_new_ptr();
















@@ -2841,14 +2843,16 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)















static inline int get_fp_bit(int cc)









{









    if (cc)









    if (cc) {









        return 24 + cc;









    else









    } else {









        return 23;









    }









}

















/* Addresses computation */









static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)









static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0,









                                   TCGv arg1)









{









    tcg_gen_add_tl(ret, arg0, arg1);
















@@ -2907,15 +2911,17 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)















static inline void check_cp0_enabled(DisasContext *ctx)









{









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {









        generate_exception_err(ctx, EXCP_CpU, 0);









    }









}

















static inline void check_cp1_enabled(DisasContext *ctx)









{









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {









        generate_exception_err(ctx, EXCP_CpU, 1);









    }









}

















/* Verify that the processor is running with COP1X instructions enabled.









   This is associated with the nabla symbol in the MIPS32 and MIPS64








@@ -2923,18 +2929,20 @@ static inline void check_cp1_enabled(DisasContext *ctx)















static inline void check_cop1x(DisasContext *ctx)









{









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {









        generate_exception_end(ctx, EXCP_RI);









    }









}

















/* Verify that the processor is running with 64-bit floating-point









   operations enabled.  */

















static inline void check_cp1_64bitmode(DisasContext *ctx)









{









    if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))









    if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {









        generate_exception_end(ctx, EXCP_RI);









    }









}

















/*









 * Verify if floating point register is valid; an operation is not defined








@@ -2949,9 +2957,10 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)







 */









static inline void check_cp1_registers(DisasContext *ctx, int regs)









{









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {









        generate_exception_end(ctx, EXCP_RI);









    }









}

















/* Verify that the processor is running with DSP instructions enabled.









   This is enabled by CP0 Status register MX(24) bit.








@@ -3039,9 +3048,10 @@ static inline void check_ps(DisasContext *ctx)







   instructions are not enabled. */









static inline void check_mips_64(DisasContext *ctx)









{









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {









        generate_exception_end(ctx, EXCP_RI);









    }









}









#endif

















#ifndef CONFIG_USER_ONLY








@@ -3125,13 +3135,12 @@ static inline void check_nms(DisasContext *ctx)







 */









static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)









{









    if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&









    if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&









                 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&









                 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&









                 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&









                 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&









        !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))









    {









                 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {









        generate_exception_end(ctx, EXCP_RI);









    }









}








@@ -3179,23 +3188,56 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n,      \







    gen_ldcmp_fpr##bits (ctx, fp0, fs);                                       \









    gen_ldcmp_fpr##bits (ctx, fp1, ft);                                       \









    switch (n) {                                                              \









    case  0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc);    break;\









    case  1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc);   break;\









    case  2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc);   break;\









    case  3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc);  break;\









    case  4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc);  break;\









    case  5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc);  break;\









    case  6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc);  break;\









    case  7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc);  break;\









    case  8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc);   break;\









    case  9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\









    case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc);  break;\









    case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc);  break;\









    case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc);   break;\









    case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc);  break;\









    case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc);   break;\









    case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc);  break;\









    default: abort();                                                         \









    case  0:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc);         \









    break;                                                                    \









    case  1:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc);        \









    break;                                                                    \









    case  2:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc);        \









    break;                                                                    \









    case  3:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc);       \









    break;                                                                    \









    case  4:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc);       \









    break;                                                                    \









    case  5:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc);       \









    break;                                                                    \









    case  6:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc);       \









    break;                                                                    \









    case  7:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc);       \









    break;                                                                    \









    case  8:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc);        \









    break;                                                                    \









    case  9:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc);      \









    break;                                                                    \









    case 10:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc);       \









    break;                                                                    \









    case 11:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc);       \









    break;                                                                    \









    case 12:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc);        \









    break;                                                                    \









    case 13:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc);       \









    break;                                                                    \









    case 14:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc);        \









    break;                                                                    \









    case 15:                                                                  \









        gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc);       \









    break;                                                                    \









    default:                                                                  \









        abort();                                                              \









    }                                                                         \









    tcg_temp_free_i##bits (fp0);                                              \









    tcg_temp_free_i##bits (fp1);                                              \








@@ -3881,22 +3923,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,







    uimm = (uint16_t)imm;









    switch (opc) {









    case OPC_ANDI:









        if (likely(rs != 0))









        if (likely(rs != 0)) {









            tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);









        else









        } else {









            tcg_gen_movi_tl(cpu_gpr[rt], 0);









        }









        break;









    case OPC_ORI:









        if (rs != 0)









        if (rs != 0) {









            tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);









        else









        } else {









            tcg_gen_movi_tl(cpu_gpr[rt], uimm);









        }









        break;









    case OPC_XORI:









        if (likely(rs != 0))









        if (likely(rs != 0)) {









            tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);









        else









        } else {









            tcg_gen_movi_tl(cpu_gpr[rt], uimm);









        }









        break;









    case OPC_LUI:









        if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {








@@ -6059,8 +6104,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,







    }

















 out:









    if (insn_bytes == 2)









    if (insn_bytes == 2) {









        ctx->hflags |= MIPS_HFLAG_B16;









    }









    tcg_temp_free(t0);









    tcg_temp_free(t1);









}








@@ -6707,8 +6753,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)







{









    const char *register_name = "invalid";

















    if (sel != 0)









    if (sel != 0) {









        check_insn(ctx, ISA_MIPS32);









    }

















    switch (reg) {









    case CP0_REGISTER_00:








@@ -7463,8 +7510,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)







{









    const char *register_name = "invalid";

















    if (sel != 0)









    if (sel != 0) {









        check_insn(ctx, ISA_MIPS32);









    }

















    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {









        gen_io_start();








@@ -8209,8 +8257,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)







{









    const char *register_name = "invalid";

















    if (sel != 0)









    if (sel != 0) {









        check_insn(ctx, ISA_MIPS64);









    }

















    switch (reg) {









    case CP0_REGISTER_00:








@@ -8919,8 +8968,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)







{









    const char *register_name = "invalid";

















    if (sel != 0)









    if (sel != 0) {









        check_insn(ctx, ISA_MIPS64);









    }

















    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {









        gen_io_start();








@@ -9657,12 +9707,12 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,















    if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&









        ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=









         (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))









         (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {









        tcg_gen_movi_tl(t0, -1);









    else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >









             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))









    } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >









               (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {









        tcg_gen_movi_tl(t0, -1);









    else if (u == 0) {









    } else if (u == 0) {









        switch (rt) {









        case 1:









            switch (sel) {








@@ -9882,12 +9932,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,







    gen_load_gpr(t0, rt);









    if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&









        ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=









         (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))









         (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {









        /* NOP */ ;









    else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >









             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))









    } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >









             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {









        /* NOP */ ;









    else if (u == 0) {









    } else if (u == 0) {









        switch (rd) {









        case 1:









            switch (sel) {








@@ -10077,7 +10127,8 @@ die:







    generate_exception_end(ctx, EXCP_RI);









}

















static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)









static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,









                    int rt, int rd)









{









    const char *opn = "ldst";
















@@ -10160,8 +10211,9 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,







        break;









    case OPC_TLBWI:









        opn = "tlbwi";









        if (!env->tlb->helper_tlbwi)









        if (!env->tlb->helper_tlbwi) {









            goto die;









        }









        gen_helper_tlbwi(cpu_env);









        break;









    case OPC_TLBINV:








@@ -10184,20 +10236,23 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,







        break;









    case OPC_TLBWR:









        opn = "tlbwr";









        if (!env->tlb->helper_tlbwr)









        if (!env->tlb->helper_tlbwr) {









            goto die;









        }









        gen_helper_tlbwr(cpu_env);









        break;









    case OPC_TLBP:









        opn = "tlbp";









        if (!env->tlb->helper_tlbp)









        if (!env->tlb->helper_tlbp) {









            goto die;









        }









        gen_helper_tlbp(cpu_env);









        break;









    case OPC_TLBR:









        opn = "tlbr";









        if (!env->tlb->helper_tlbr)









        if (!env->tlb->helper_tlbr) {









            goto die;









        }









        gen_helper_tlbr(cpu_env);









        break;









    case OPC_ERET: /* OPC_ERETNC */








@@ -10271,8 +10326,9 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,







        goto out;









    }

















    if (cc != 0)









    if (cc != 0) {









        check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);









    }

















    btarget = ctx->base.pc_next + 4 + offset;
















@@ -10633,6 +10689,7 @@ enum r6_f_cmp_op {







    R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),









    R6_OPC_CMP_SNE_D  = FOP(27, FMT_L),









};

















static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)









{









    TCGv t0 = tcg_temp_new();








@@ -10725,10 +10782,11 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)







        return;









    }

















    if (tf)









    if (tf) {









        cond = TCG_COND_EQ;









    else









    } else {









        cond = TCG_COND_NE;









    }

















    l1 = gen_new_label();









    t0 = tcg_temp_new_i32();








@@ -10750,10 +10808,11 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,







    TCGv_i32 t0 = tcg_temp_new_i32();









    TCGLabel *l1 = gen_new_label();

















    if (tf)









    if (tf) {









        cond = TCG_COND_EQ;









    else









    } else {









        cond = TCG_COND_NE;









    }

















    tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));









    tcg_gen_brcondi_i32(cond, t0, 0, l1);








@@ -10763,17 +10822,19 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,







    tcg_temp_free_i32(t0);









}

















static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)









static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,









                               int tf)









{









    int cond;









    TCGv_i32 t0 = tcg_temp_new_i32();









    TCGv_i64 fp0;









    TCGLabel *l1 = gen_new_label();

















    if (tf)









    if (tf) {









        cond = TCG_COND_EQ;









    else









    } else {









        cond = TCG_COND_NE;









    }

















    tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));









    tcg_gen_brcondi_i32(cond, t0, 0, l1);








@@ -10793,10 +10854,11 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,







    TCGLabel *l1 = gen_new_label();









    TCGLabel *l2 = gen_new_label();

















    if (tf)









    if (tf) {









        cond = TCG_COND_EQ;









    else









    } else {









        cond = TCG_COND_NE;









    }

















    tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));









    tcg_gen_brcondi_i32(cond, t0, 0, l1);








@@ -12092,8 +12154,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,







            TCGLabel *l1 = gen_new_label();









            TCGv_i64 fp0;

















            if (ft != 0)









            if (ft != 0) {









                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);









            }









            fp0 = tcg_temp_new_i64();









            gen_load_fpr64(ctx, fp0, fs);









            gen_store_fpr64(ctx, fp0, fd);








@@ -29987,13 +30050,15 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)







                 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],









                 env->hflags, env->btarget, env->bcond);









    for (i = 0; i < 32; i++) {









        if ((i & 3) == 0)









        if ((i & 3) == 0) {









            qemu_fprintf(f, "GPR%02d:", i);









        }









        qemu_fprintf(f, " %s " TARGET_FMT_lx,









                     regnames[i], env->active_tc.gpr[i]);









        if ((i & 3) == 3)









        if ((i & 3) == 3) {









            qemu_fprintf(f, "\n");









        }









    }

















    qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",









                 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);

























tests/tcg/mips/include/test_utils_128.h



+10
−7




























File changed.
Preview size limit exceeded, changes collapsed.
























tests/tcg/mips/include/test_utils_64.h



+6
−3






























Original line number
Diff line number
Diff line







@@ -30,7 +30,9 @@







#define PRINT_RESULTS 0





























static inline int32_t check_results_64(const char *instruction_name,









static inline int32_t check_results_64(const char *isa_ase_name,









                                       const char *group_name,









                                       const char *instruction_name,









                                       const uint32_t test_count,









                                       const double elapsed_time,









                                       const uint64_t *b64_result,








@@ -55,7 +57,8 @@ static inline int32_t check_results_64(const char *instruction_name,







    uint32_t pass_count = 0;









    uint32_t fail_count = 0;



















    printf("%s:   ", instruction_name);









    printf("| %-10s \t| %-20s\t| %-16s \t|",









           isa_ase_name, group_name, instruction_name);









    for (i = 0; i < test_count; i++) {









        if (b64_result[i] == b64_expect[i]) {









            pass_count++;








@@ -64,7 +67,7 @@ static inline int32_t check_results_64(const char *instruction_name,







        }









    }



















    printf("PASS: %3d   FAIL: %3d   elapsed time: %5.2f ms\n",









    printf(" PASS: %3d \t| FAIL: %3d \t| elapsed time: %5.2f ms \t|\n",









           pass_count, fail_count, elapsed_time);



















    if (fail_count > 0) {