Merge remote-tracking branch 'remotes/rth/tags/tgt-openrisc-pull-request' into staging (46cc2fc4) · Commits · SUMMER2020 / students / proj-2021291

target/openrisc/Makefile.objs

+9 −0

Original line number	Diff line number	Diff line
		@@ -3,3 +3,12 @@ obj-y += cpu.o exception.o interrupt.o mmu.o translate.o
		obj-y += exception_helper.o fpu_helper.o \
		interrupt_helper.o mmu_helper.o sys_helper.o
		obj-y += gdbstub.o

		DECODETREE = $(SRC_PATH)/scripts/decodetree.py

		target/openrisc/decode.inc.c: \
		$(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)
		$(call quiet-command,\
		$(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)

		target/openrisc/translate.o: target/openrisc/decode.inc.c

target/openrisc/fpu_helper.c

+49 −203

Original line number	Diff line number	Diff line
		@@ -24,121 +24,70 @@
		#include "exception.h"
		#include "fpu/softfloat.h"

		static inline uint32_t ieee_ex_to_openrisc(OpenRISCCPU *cpu, int fexcp)
		static int ieee_ex_to_openrisc(int fexcp)
		{
		int ret = 0;
		if (fexcp) {
		if (fexcp & float_flag_invalid) {
		cpu->env.fpcsr \|= FPCSR_IVF;
		ret = 1;
		ret \|= FPCSR_IVF;
		}
		if (fexcp & float_flag_overflow) {
		cpu->env.fpcsr \|= FPCSR_OVF;
		ret = 1;
		ret \|= FPCSR_OVF;
		}
		if (fexcp & float_flag_underflow) {
		cpu->env.fpcsr \|= FPCSR_UNF;
		ret = 1;
		ret \|= FPCSR_UNF;
		}
		if (fexcp & float_flag_divbyzero) {
		cpu->env.fpcsr \|= FPCSR_DZF;
		ret = 1;
		ret \|= FPCSR_DZF;
		}
		if (fexcp & float_flag_inexact) {
		cpu->env.fpcsr \|= FPCSR_IXF;
		ret = 1;
		ret \|= FPCSR_IXF;
		}
		}

		return ret;
		}

		static inline void update_fpcsr(OpenRISCCPU *cpu)
		void HELPER(update_fpcsr)(CPUOpenRISCState *env)
		{
		int tmp = ieee_ex_to_openrisc(cpu,
		get_float_exception_flags(&cpu->env.fp_status));
		int tmp = get_float_exception_flags(&env->fp_status);

		SET_FP_CAUSE(cpu->env.fpcsr, tmp);
		if ((GET_FP_ENABLE(cpu->env.fpcsr) & tmp) &&
		(cpu->env.fpcsr & FPCSR_FPEE)) {
		helper_exception(&cpu->env, EXCP_FPE);
		} else {
		UPDATE_FP_FLAGS(cpu->env.fpcsr, tmp);
		if (tmp) {
		set_float_exception_flags(0, &env->fp_status);
		tmp = ieee_ex_to_openrisc(tmp);
		if (tmp) {
		env->fpcsr \|= tmp;
		if (env->fpcsr & FPCSR_FPEE) {
		helper_exception(env, EXCP_FPE);
		}
		}
		}
		}

		uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
		{
		uint64_t itofd;
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

		set_float_exception_flags(0, &cpu->env.fp_status);
		itofd = int32_to_float64(val, &cpu->env.fp_status);
		update_fpcsr(cpu);

		return itofd;
		return int32_to_float64(val, &env->fp_status);
		}

		uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
		{
		uint32_t itofs;
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

		set_float_exception_flags(0, &cpu->env.fp_status);
		itofs = int32_to_float32(val, &cpu->env.fp_status);
		update_fpcsr(cpu);

		return itofs;
		return int32_to_float32(val, &env->fp_status);
		}

		uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
		{
		uint64_t ftoid;
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

		set_float_exception_flags(0, &cpu->env.fp_status);
		ftoid = float32_to_int64(val, &cpu->env.fp_status);
		update_fpcsr(cpu);

		return ftoid;
		return float32_to_int64(val, &env->fp_status);
		}

		uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
		{
		uint32_t ftois;
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

		set_float_exception_flags(0, &cpu->env.fp_status);
		ftois = float32_to_int32(val, &cpu->env.fp_status);
		update_fpcsr(cpu);

		return ftois;
		return float32_to_int32(val, &env->fp_status);
		}

		#define FLOAT_OP(name, p) void helper_float_##_##p(void)

		#define FLOAT_CALC(name) \
		uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
		uint64_t fdt0, uint64_t fdt1) \
		{ \
		uint64_t result; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return result; \
		} \
		\
		{ return float64_ ## name(fdt0, fdt1, &env->fp_status); } \
		uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
		uint32_t fdt0, uint32_t fdt1) \
		{ \
		uint32_t result; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return result; \
		} \
		{ return float32_ ## name(fdt0, fdt1, &env->fp_status); }

		FLOAT_CALC(add)
		FLOAT_CALC(sub)
		@@ -151,132 +100,29 @@ FLOAT_CALC(rem)
		uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a,
		uint64_t b, uint64_t c)
		{
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
		uint64_t result;
		set_float_exception_flags(0, &cpu->env.fp_status);
		/* Note that or1ksim doesn't use merged operation. */
		result = float64_mul(b, c, &cpu->env.fp_status);
		result = float64_add(result, a, &cpu->env.fp_status);
		update_fpcsr(cpu);
		return result;
		/* Note that or1ksim doesn't use fused operation. */
		b = float64_mul(b, c, &env->fp_status);
		return float64_add(a, b, &env->fp_status);
		}

		uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
		uint32_t b, uint32_t c)
		{
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
		uint32_t result;
		set_float_exception_flags(0, &cpu->env.fp_status);
		/* Note that or1ksim doesn't use merged operation. */
		result = float32_mul(b, c, &cpu->env.fp_status);
		result = float32_add(result, a, &cpu->env.fp_status);
		update_fpcsr(cpu);
		return result;
		/* Note that or1ksim doesn't use fused operation. */
		b = float32_mul(b, c, &env->fp_status);
		return float32_add(a, b, &env->fp_status);
		}


		#define FLOAT_CMP(name) \
		uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
		#define FLOAT_CMP(name, impl) \
		target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
		uint64_t fdt0, uint64_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		} \
		\
		uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
		{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \
		target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
		uint32_t fdt0, uint32_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		}
		{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); }

		FLOAT_CMP(le)
		FLOAT_CMP(eq)
		FLOAT_CMP(lt)
		FLOAT_CMP(le, le)
		FLOAT_CMP(lt, lt)
		FLOAT_CMP(eq, eq_quiet)
		#undef FLOAT_CMP


		#define FLOAT_CMPNE(name) \
		uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
		uint64_t fdt0, uint64_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = !float64_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		} \
		\
		uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
		uint32_t fdt0, uint32_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = !float32_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		}

		FLOAT_CMPNE(ne)
		#undef FLOAT_CMPNE

		#define FLOAT_CMPGT(name) \
		uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
		uint64_t fdt0, uint64_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = !float64_le(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		} \
		\
		uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
		uint32_t fdt0, uint32_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = !float32_le(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		}
		FLOAT_CMPGT(gt)
		#undef FLOAT_CMPGT

		#define FLOAT_CMPGE(name) \
		uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
		uint64_t fdt0, uint64_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = !float64_lt(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		} \
		\
		uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
		uint32_t fdt0, uint32_t fdt1) \
		{ \
		int res; \
		OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
		set_float_exception_flags(0, &cpu->env.fp_status); \
		res = !float32_lt(fdt0, fdt1, &cpu->env.fp_status); \
		update_fpcsr(cpu); \
		return res; \
		}

		FLOAT_CMPGE(ge)
		#undef FLOAT_CMPGE

target/openrisc/helper.h

+12 −13

Original line number	Diff line number	Diff line
		@@ -24,17 +24,19 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env)
		DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env)

		/* float */
		DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64)
		DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32)
		DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64)
		DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32)
		DEF_HELPER_FLAGS_1(update_fpcsr, TCG_CALL_NO_WG, void, env)

		DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32)
		DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
		DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64)
		DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32)
		DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64)
		DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32)

		DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)
		DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)

		#define FOP_CALC(op) \
		DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \
		DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64)
		DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32) \
		DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i64, env, i64, i64)
		FOP_CALC(add)
		FOP_CALC(sub)
		FOP_CALC(mul)
		@@ -43,14 +45,11 @@ FOP_CALC(rem)
		#undef FOP_CALC

		#define FOP_CMP(op) \
		DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \
		DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64)
		DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32) \
		DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64)
		FOP_CMP(eq)
		FOP_CMP(lt)
		FOP_CMP(le)
		FOP_CMP(ne)
		FOP_CMP(gt)
		FOP_CMP(ge)
		#undef FOP_CMP

		/* interrupt */

target/openrisc/insns.decode

0 → 100644

+189 −0

Original line number	Diff line number	Diff line
		#
		# OpenRISC instruction decode definitions.
		#
		# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
		#
		# This library is free software; you can redistribute it and/or
		# modify it under the terms of the GNU Lesser General Public
		# License as published by the Free Software Foundation; either
		# version 2 of the License, or (at your option) any later version.
		#
		# This library is distributed in the hope that it will be useful,
		# but WITHOUT ANY WARRANTY; without even the implied warranty of
		# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		# Lesser General Public License for more details.
		#
		# You should have received a copy of the GNU Lesser General Public
		# License along with this library; if not, see <http://www.gnu.org/licenses/>.
		#

		&dab d a b
		&da d a
		&ab a b
		&dal d a l
		&ai a i

		####
		# System Instructions
		####

		l_sys 001000 0000000000 k:16
		l_trap 001000 0100000000 k:16
		l_msync 001000 1000000000 00000000 00000000
		l_psync 001000 1010000000 00000000 00000000
		l_csync 001000 1100000000 00000000 00000000

		l_rfe 001001 ----- ----- -------- --------

		####
		# Branch Instructions
		####

		l_j 000000 n:s26
		l_jal 000001 n:s26
		l_bnf 000011 n:s26
		l_bf 000100 n:s26

		l_jr 010001 ---------- b:5 -----------
		l_jalr 010010 ---------- b:5 -----------

		####
		# Memory Instructions
		####

		&load d a i
		@load ...... d:5 a:5 i:s16 &load

		%store_i 21:s5 0:11
		&store a b i
		@store ...... ..... a:5 b:5 ........... &store i=%store_i

		l_lwa 011011 ..... ..... ........ ........ @load
		l_lwz 100001 ..... ..... ........ ........ @load
		l_lws 100010 ..... ..... ........ ........ @load
		l_lbz 100011 ..... ..... ........ ........ @load
		l_lbs 100100 ..... ..... ........ ........ @load
		l_lhz 100101 ..... ..... ........ ........ @load
		l_lhs 100110 ..... ..... ........ ........ @load

		l_swa 110011 ..... ..... ..... ........... @store
		l_sw 110101 ..... ..... ..... ........... @store
		l_sb 110110 ..... ..... ..... ........... @store
		l_sh 110111 ..... ..... ..... ........... @store

		####
		# Immediate Operand Instructions
		####

		%mtspr_k 21:5 0:11

		&rri d a i
		&rrk d a k
		@rri ...... d:5 a:5 i:s16 &rri
		@rrk ...... d:5 a:5 k:16 &rrk

		l_nop 000101 01--- ----- k:16

		l_addi 100111 ..... ..... ........ ........ @rri
		l_addic 101000 ..... ..... ........ ........ @rri
		l_andi 101001 ..... ..... ........ ........ @rrk
		l_ori 101010 ..... ..... ........ ........ @rrk
		l_xori 101011 ..... ..... ........ ........ @rri
		l_muli 101100 ..... ..... ........ ........ @rri

		l_mfspr 101101 ..... ..... ........ ........ @rrk
		l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k

		l_maci 010011 ----- a:5 i:s16

		l_movhi 000110 d:5 ----0 k:16
		l_macrc 000110 d:5 ----1 00000000 00000000

		####
		# Arithmetic Instructions
		####

		l_exths 111000 d:5 a:5 ----- - 0000 -- 1100
		l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100
		l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100
		l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100

		l_add 111000 d:5 a:5 b:5 - 00 ---- 0000
		l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001
		l_sub 111000 d:5 a:5 b:5 - 00 ---- 0010
		l_and 111000 d:5 a:5 b:5 - 00 ---- 0011
		l_or 111000 d:5 a:5 b:5 - 00 ---- 0100
		l_xor 111000 d:5 a:5 b:5 - 00 ---- 0101
		l_cmov 111000 d:5 a:5 b:5 - 00 ---- 1110
		l_ff1 111000 d:5 a:5 ----- - 00 ---- 1111
		l_fl1 111000 d:5 a:5 ----- - 01 ---- 1111

		l_sll 111000 d:5 a:5 b:5 - 0000 -- 1000
		l_srl 111000 d:5 a:5 b:5 - 0001 -- 1000
		l_sra 111000 d:5 a:5 b:5 - 0010 -- 1000
		l_ror 111000 d:5 a:5 b:5 - 0011 -- 1000

		l_mul 111000 d:5 a:5 b:5 - 11 ---- 0110
		l_mulu 111000 d:5 a:5 b:5 - 11 ---- 1011
		l_div 111000 d:5 a:5 b:5 - 11 ---- 1001
		l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010

		l_muld 111000 ----- a:5 b:5 - 11 ---- 0111
		l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100

		l_mac 110001 ----- a:5 b:5 ------- 0001
		l_macu 110001 ----- a:5 b:5 ------- 0011
		l_msb 110001 ----- a:5 b:5 ------- 0010
		l_msbu 110001 ----- a:5 b:5 ------- 0100

		l_slli 101110 d:5 a:5 -------- 00 l:6
		l_srli 101110 d:5 a:5 -------- 01 l:6
		l_srai 101110 d:5 a:5 -------- 10 l:6
		l_rori 101110 d:5 a:5 -------- 11 l:6

		####
		# Compare Instructions
		####

		l_sfeq 111001 00000 a:5 b:5 -----------
		l_sfne 111001 00001 a:5 b:5 -----------
		l_sfgtu 111001 00010 a:5 b:5 -----------
		l_sfgeu 111001 00011 a:5 b:5 -----------
		l_sfltu 111001 00100 a:5 b:5 -----------
		l_sfleu 111001 00101 a:5 b:5 -----------
		l_sfgts 111001 01010 a:5 b:5 -----------
		l_sfges 111001 01011 a:5 b:5 -----------
		l_sflts 111001 01100 a:5 b:5 -----------
		l_sfles 111001 01101 a:5 b:5 -----------

		l_sfeqi 101111 00000 a:5 i:s16
		l_sfnei 101111 00001 a:5 i:s16
		l_sfgtui 101111 00010 a:5 i:s16
		l_sfgeui 101111 00011 a:5 i:s16
		l_sfltui 101111 00100 a:5 i:s16
		l_sfleui 101111 00101 a:5 i:s16
		l_sfgtsi 101111 01010 a:5 i:s16
		l_sfgesi 101111 01011 a:5 i:s16
		l_sfltsi 101111 01100 a:5 i:s16
		l_sflesi 101111 01101 a:5 i:s16

		####
		# FP Instructions
		####

		lf_add_s 110010 d:5 a:5 b:5 --- 00000000
		lf_sub_s 110010 d:5 a:5 b:5 --- 00000001
		lf_mul_s 110010 d:5 a:5 b:5 --- 00000010
		lf_div_s 110010 d:5 a:5 b:5 --- 00000011
		lf_rem_s 110010 d:5 a:5 b:5 --- 00000110
		lf_madd_s 110010 d:5 a:5 b:5 --- 00000111

		lf_itof_s 110010 d:5 a:5 00000 --- 00000100
		lf_ftoi_s 110010 d:5 a:5 00000 --- 00000101

		lf_sfeq_s 110010 ----- a:5 b:5 --- 00001000
		lf_sfne_s 110010 ----- a:5 b:5 --- 00001001
		lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010
		lf_sfge_s 110010 ----- a:5 b:5 --- 00001011
		lf_sflt_s 110010 ----- a:5 b:5 --- 00001100
		lf_sfle_s 110010 ----- a:5 b:5 --- 00001101

target/openrisc/translate.c

+791 −935

File changed.

Preview size limit exceeded, changes collapsed.