Commit 45db7ba6 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Make VTOR register banked for v8M 



Make the VTOR register banked if v8M security extensions are enabled.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org
parent f104919d

hw/intc/armv7m_nvic.c

+7 −6
Original line number Diff line number Diff line
@@ -403,7 +403,7 @@ static void set_irq_level(void *opaque, int n, int level) 
    }

}



static uint32_t nvic_readl(NVICState *s, uint32_t offset)

static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

{

    ARMCPU *cpu = s->cpu;

    uint32_t val;
@@ -441,7 +441,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) 
        /* ISRPREEMPT not implemented */

        return val;

    case 0xd08: /* Vector Table Offset.  */

        return cpu->env.v7m.vecbase;

        return cpu->env.v7m.vecbase[attrs.secure];

    case 0xd0c: /* Application Interrupt/Reset Control.  */

        return 0xfa050000 | (s->prigroup << 8);

    case 0xd10: /* System Control.  */
@@ -617,7 +617,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) 
    }

}



static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)

static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

                        MemTxAttrs attrs)

{

    ARMCPU *cpu = s->cpu;
@@ -638,7 +639,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) 
        }

        break;

    case 0xd08: /* Vector Table Offset.  */

        cpu->env.v7m.vecbase = value & 0xffffff80;

        cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;

        break;

    case 0xd0c: /* Application Interrupt/Reset Control.  */

        if ((value >> 16) == 0x05fa) {
@@ -944,7 +945,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 
        break;

    default:

        if (size == 4) {

            val = nvic_readl(s, offset);

            val = nvic_readl(s, offset, attrs);

        } else {

            qemu_log_mask(LOG_GUEST_ERROR,

                          "NVIC: Bad read of size %d at offset 0x%x\n",
@@ -1025,7 +1026,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
        return MEMTX_OK;

    }

    if (size == 4) {

        nvic_writel(s, offset, value);

        nvic_writel(s, offset, value, attrs);

        return MEMTX_OK;

    }

    qemu_log_mask(LOG_GUEST_ERROR,

target/arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -420,7 +420,7 @@ typedef struct CPUARMState { 


    struct {

        uint32_t other_sp;

        uint32_t vecbase;

        uint32_t vecbase[2];

        uint32_t basepri[2];

        uint32_t control[2];

        uint32_t ccr; /* Configuration and Control */

target/arm/helper.c

+1 −1
Original line number Diff line number Diff line
@@ -6067,7 +6067,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) 
    CPUState *cs = CPU(cpu);

    CPUARMState *env = &cpu->env;

    MemTxResult result;

    hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4;

    hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4;

    uint32_t addr;



    addr = address_space_ldl(cs->as, vec,

target/arm/machine.c

+2 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ static const VMStateDescription vmstate_m = { 
    .minimum_version_id = 4,

    .needed = m_needed,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),

        VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),

        VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),

        VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),

        VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
@@ -254,6 +254,7 @@ static const VMStateDescription vmstate_m_security = { 
        VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),

        VMSTATE_END_OF_LIST()

    }

};