Commit 42747d6a authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch... 


Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-06-15.for-upstream' into staging

xilinx-next-2018-06-15.for-upstream

# gpg: Signature made Fri 15 Jun 2018 15:32:47 BST
# gpg:                using RSA key 29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>"
# gpg:                 aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF  4151 29C5 9678 0F6B CA83

* remotes/edgar/tags/edgar/xilinx-next-2018-06-15.for-upstream:
  target-microblaze: Rework NOP/zero instruction handling
  target-microblaze: mmu: Correct masking of output addresses

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 4359255a 462c2544

target/microblaze/mmu.c

+0 −1
Original line number Diff line number Diff line
@@ -159,7 +159,6 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, 


            lu->vaddr = tlb_tag;

            lu->paddr = tlb_rpn & mmu->c_addr_mask;

            lu->paddr = tlb_rpn;

            lu->size = tlb_size;

            lu->err = ERR_HIT;

            lu->idx = i;

target/microblaze/translate.c

+4 −11
Original line number Diff line number Diff line
@@ -90,7 +90,6 @@ typedef struct DisasContext { 
    uint32_t jmp_pc;



    int abort_at_next_insn;

    int nr_nops;

    struct TranslationBlock *tb;

    int singlestep_enabled;

} DisasContext;
@@ -1576,17 +1575,12 @@ static inline void decode(DisasContext *dc, uint32_t ir) 
    dc->ir = ir;

    LOG_DIS("%8.8x\t", dc->ir);



    if (dc->ir)

        dc->nr_nops = 0;

    else {

    if (ir == 0) {

        trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);



        LOG_DIS("nr_nops=%d\t", dc->nr_nops);

        dc->nr_nops++;

        if (dc->nr_nops > 4) {

            cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");

        }

        /* Don't decode nop/zero instructions any further.  */

        return;

    }



    /* bit 2 seems to indicate insn type.  */

    dc->type_b = ir & (1 << 29);
@@ -1633,7 +1627,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 
    dc->singlestep_enabled = cs->singlestep_enabled;

    dc->cpustate_changed = 0;

    dc->abort_at_next_insn = 0;

    dc->nr_nops = 0;



    if (pc_start & 3) {

        cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);