Commit 426d0e7b authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150804' into staging 



MIPS patches 2015-08-04

Changes:
* fix semihosting for microMIPS R6
* fix an abort when booting mips64 kernel with --enable-tcg-debug

# gpg: Signature made Tue 04 Aug 2015 12:32:17 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150804:
  target-mips: Copy restrictions from ext/ins to dext/dins
  target-mips: fix semihosting for microMIPS R6

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 260425ab b7f26e52

target-mips/translate.c

+32 −23
Original line number Diff line number Diff line
@@ -4750,48 +4750,53 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, 
    gen_load_gpr(t1, rs);

    switch (opc) {

    case OPC_EXT:

        if (lsb + msb > 31)

        if (lsb + msb > 31) {

            goto fail;

        }

        tcg_gen_shri_tl(t0, t1, lsb);

        if (msb != 31) {

            tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);

            tcg_gen_andi_tl(t0, t0, (1U << (msb + 1)) - 1);

        } else {

            tcg_gen_ext32s_tl(t0, t0);

        }

        break;

#if defined(TARGET_MIPS64)

    case OPC_DEXTM:

        tcg_gen_shri_tl(t0, t1, lsb);

        if (msb != 31) {

            tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1);

        }

        break;

    case OPC_DEXTU:

        tcg_gen_shri_tl(t0, t1, lsb + 32);

        tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);

        break;

        lsb += 32;

        goto do_dext;

    case OPC_DEXTM:

        msb += 32;

        goto do_dext;

    case OPC_DEXT:

    do_dext:

        if (lsb + msb > 63) {

            goto fail;

        }

        tcg_gen_shri_tl(t0, t1, lsb);

        if (msb != 63) {

            tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);

        }

        break;

#endif

    case OPC_INS:

        if (lsb > msb)

        if (lsb > msb) {

            goto fail;

        }

        gen_load_gpr(t0, rt);

        tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);

        tcg_gen_ext32s_tl(t0, t0);

        break;

#if defined(TARGET_MIPS64)

    case OPC_DINSM:

        gen_load_gpr(t0, rt);

        tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1);

        break;

    case OPC_DINSU:

        gen_load_gpr(t0, rt);

        tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1);

        break;

        lsb += 32;

        /* FALLTHRU */

    case OPC_DINSM:

        msb += 32;

        /* FALLTHRU */

    case OPC_DINS:

        if (lsb > msb) {

            goto fail;

        }

        gen_load_gpr(t0, rt);

        tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);

        break;
@@ -13278,11 +13283,15 @@ static void gen_pool16c_r6_insn(DisasContext *ctx) 
            break;

        case R6_SDBBP16:

            /* SDBBP16 */

            if (is_uhi(extract32(ctx->opcode, 6, 4))) {

                gen_helper_do_semihosting(cpu_env);

            } else {

                if (ctx->hflags & MIPS_HFLAG_SBRI) {

                    generate_exception(ctx, EXCP_RI);

                } else {

                    generate_exception(ctx, EXCP_DBp);

                }

            }

            break;

        }

        break;