Commit 425591e3 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150813' into staging 



target-arm queue:
 * i.MX code cleanup/refactorings
 * i.MX UART fix to work with uninitialized chardev
 * minor GIC code refactorings
 * implement the ARM Secure physical timer
 * implement the ARM Hypervisor timer

# gpg: Signature made Thu 13 Aug 2015 11:40:56 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150813: (27 commits)
  i.MX: Fix UART driver to work with unitialized "chardev" device
  hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
  hw/arm/virt: Wire up secure timer interrupt
  target-arm: Add AArch32 banked register access to secure physical timer
  target-arm: Add the AArch64 view of the Secure physical timer
  target-arm: Add debug check for mismatched cpreg resets
  Introduce gic_class_name() instead of repeating condition
  hw/arm/gic: Kill code duplication
  Merge memory_region_init_reservation() into memory_region_init_io()
  i.MX: Fix Coding style for GPT emulator
  i.MX: Split GPT emulator in a header file and a source file
  i.MX: Fix Coding style for EPIT emulator
  i.MX: Split EPIT emulator in a header file and a source file
  i.MX: Fix Coding style for CCM emulator
  i.MX: Split CCM emulator in a header file and a source file
  i.MX: Fix Coding style for AVIC emulator.
  i.MX: Split AVIC emulator in a header file and a source file
  i.MX:Fix Coding style for UART emulator.
  i.MX: Move serial initialization to init/realize of DeviceClass.
  i.MX: Split UART emulator in a header file and a source file
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents ca0e5d8b f7a6785e

hw/arm/kzm.c

+3 −2
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include "sysemu/sysemu.h"

#include "hw/boards.h"

#include "hw/char/serial.h"

#include "hw/intc/imx_avic.h"

#include "hw/arm/imx.h"



    /* Memory map for Kzm Emulation Baseboard:
@@ -106,7 +107,7 @@ static void kzm_init(MachineState *machine) 
    memory_region_init_ram(sram, NULL, "kzm.sram", 0x4000, &error_abort);

    memory_region_add_subregion(address_space_mem, 0x1FFFC000, sram);



    dev = sysbus_create_varargs("imx_avic", 0x68000000,

    dev = sysbus_create_varargs(TYPE_IMX_AVIC, 0x68000000,

                                qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),

                                qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),

                                NULL);
@@ -114,7 +115,7 @@ static void kzm_init(MachineState *machine) 
    imx_serial_create(0, 0x43f90000, qdev_get_gpio_in(dev, 45));

    imx_serial_create(1, 0x43f94000, qdev_get_gpio_in(dev, 32));



    ccm = sysbus_create_simple("imx_ccm", 0x53f80000, NULL);

    ccm = sysbus_create_simple(TYPE_IMX_CCM, 0x53f80000, NULL);



    imx_timerp_create(0x53f94000, qdev_get_gpio_in(dev, 28), ccm);

    imx_timerp_create(0x53f98000, qdev_get_gpio_in(dev, 27), ccm);

hw/arm/virt.c

+20 −12
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 
#include "hw/arm/sysbus-fdt.h"

#include "hw/platform-bus.h"

#include "hw/arm/fdt.h"

#include "hw/intc/arm_gic_common.h"

#include "kvm_arm.h"



/* Number of external interrupt lines to configure the GIC with */

#define NUM_IRQS 256
@@ -365,12 +367,10 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) 
    /* We create a standalone GIC v2 */

    DeviceState *gicdev;

    SysBusDevice *gicbusdev;

    const char *gictype = "arm_gic";

    const char *gictype;

    int i;



    if (kvm_irqchip_in_kernel()) {

        gictype = "kvm-arm-gic";

    }

    gictype = gic_class_name();



    gicdev = qdev_create(NULL, gictype);

    qdev_prop_set_uint32(gicdev, "revision", 2);
@@ -390,15 +390,23 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) 
     */

    for (i = 0; i < smp_cpus; i++) {

        DeviceState *cpudev = DEVICE(qemu_get_cpu(i));

        int ppibase = NUM_IRQS + i * 32;

        /* physical timer; we wire it up to the non-secure timer's ID,

         * since a real A15 always has TrustZone but QEMU doesn't.

        int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;

        int irq;

        /* Mapping from the output timer irq lines from the CPU to the

         * GIC PPI inputs we use for the virt board.

         */

        qdev_connect_gpio_out(cpudev, 0,

                              qdev_get_gpio_in(gicdev, ppibase + 30));

        /* virtual timer */

        qdev_connect_gpio_out(cpudev, 1,

                              qdev_get_gpio_in(gicdev, ppibase + 27));

        const int timer_irq[] = {

            [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,

            [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,

            [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,

            [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,

        };



        for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {

            qdev_connect_gpio_out(cpudev, irq,

                                  qdev_get_gpio_in(gicdev,

                                                   ppibase + timer_irq[irq]));

        }



        sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));

        sysbus_connect_irq(gicbusdev, i + smp_cpus,

hw/char/imx_serial.c

+44 −115
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 * Copyright (c) 2008 OKL

 * Originally Written by Hans Jiang

 * Copyright (c) 2011 NICTA Pty Ltd.

 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>

 *

 * This work is licensed under the terms of the GNU GPL, version 2 or later.

 * See the COPYING file in the top-level directory.
@@ -17,8 +18,7 @@ 
 *     is a real serial device.

 */



#include "hw/hw.h"

#include "hw/sysbus.h"

#include "hw/char/imx_serial.h"

#include "sysemu/sysemu.h"

#include "sysemu/char.h"

#include "hw/arm/imx.h"
@@ -26,7 +26,7 @@ 
//#define DEBUG_SERIAL 1

#ifdef DEBUG_SERIAL

#define DPRINTF(fmt, args...) \

do { printf("imx_serial: " fmt , ##args); } while (0)

do { printf("%s: " fmt , TYPE_IMX_SERIAL, ##args); } while (0)

#else

#define DPRINTF(fmt, args...) do {} while (0)

#endif
@@ -38,42 +38,13 @@ do { printf("imx_serial: " fmt , ##args); } while (0) 
//#define DEBUG_IMPLEMENTATION 1

#ifdef DEBUG_IMPLEMENTATION

#  define IPRINTF(fmt, args...) \

    do  { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0)

    do  { fprintf(stderr, "%s: " fmt, TYPE_IMX_SERIAL, ##args); } while (0)

#else

#  define IPRINTF(fmt, args...) do {} while (0)

#endif



#define TYPE_IMX_SERIAL "imx-serial"

#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)



typedef struct IMXSerialState {

    SysBusDevice parent_obj;



    MemoryRegion iomem;

    int32_t readbuff;



    uint32_t usr1;

    uint32_t usr2;

    uint32_t ucr1;

    uint32_t ucr2;

    uint32_t uts1;



    /*

     * The registers below are implemented just so that the

     * guest OS sees what it has written

     */

    uint32_t onems;

    uint32_t ufcr;

    uint32_t ubmr;

    uint32_t ubrc;

    uint32_t ucr3;



    qemu_irq irq;

    CharDriverState *chr;

} IMXSerialState;



static const VMStateDescription vmstate_imx_serial = {

    .name = "imx-serial",

    .name = TYPE_IMX_SERIAL,

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {
@@ -91,55 +62,6 @@ static const VMStateDescription vmstate_imx_serial = { 
    },

};





#define URXD_CHARRDY    (1<<15)   /* character read is valid */

#define URXD_ERR        (1<<14)   /* Character has error */

#define URXD_BRK        (1<<11)   /* Break received */



#define USR1_PARTYER    (1<<15)   /* Parity Error */

#define USR1_RTSS       (1<<14)   /* RTS pin status */

#define USR1_TRDY       (1<<13)   /* Tx ready */

#define USR1_RTSD       (1<<12)   /* RTS delta: pin changed state */

#define USR1_ESCF       (1<<11)   /* Escape sequence interrupt */

#define USR1_FRAMERR    (1<<10)   /* Framing error  */

#define USR1_RRDY       (1<<9)    /* receiver ready */

#define USR1_AGTIM      (1<<8)    /* Aging timer interrupt */

#define USR1_DTRD       (1<<7)    /* DTR changed */

#define USR1_RXDS       (1<<6)    /* Receiver is idle */

#define USR1_AIRINT     (1<<5)    /* Aysnch IR interrupt */

#define USR1_AWAKE      (1<<4)    /* Falling edge detected on RXd pin */



#define USR2_ADET       (1<<15)   /* Autobaud complete */

#define USR2_TXFE       (1<<14)   /* Transmit FIFO empty */

#define USR2_DTRF       (1<<13)   /* DTR/DSR transition */

#define USR2_IDLE       (1<<12)   /* UART has been idle for too long */

#define USR2_ACST       (1<<11)   /* Autobaud counter stopped */

#define USR2_RIDELT     (1<<10)   /* Ring Indicator delta */

#define USR2_RIIN       (1<<9)    /* Ring Indicator Input */

#define USR2_IRINT      (1<<8)    /* Serial Infrared Interrupt */

#define USR2_WAKE       (1<<7)    /* Start bit detected */

#define USR2_DCDDELT    (1<<6)    /* Data Carrier Detect delta */

#define USR2_DCDIN      (1<<5)    /* Data Carrier Detect Input */

#define USR2_RTSF       (1<<4)    /* RTS transition */

#define USR2_TXDC       (1<<3)    /* Transmission complete */

#define USR2_BRCD       (1<<2)    /* Break condition detected */

#define USR2_ORE        (1<<1)    /* Overrun error */

#define USR2_RDR        (1<<0)    /* Receive data ready */



#define UCR1_TRDYEN     (1<<13)   /* Tx Ready Interrupt Enable */

#define UCR1_RRDYEN     (1<<9)    /* Rx Ready Interrupt Enable */

#define UCR1_TXMPTYEN   (1<<6)    /* Tx Empty Interrupt Enable */

#define UCR1_UARTEN     (1<<0)    /* UART Enable */



#define UCR2_TXEN       (1<<2)    /* Transmitter enable */

#define UCR2_RXEN       (1<<1)    /* Receiver enable */

#define UCR2_SRST       (1<<0)    /* Reset complete */



#define UTS1_TXEMPTY    (1<<6)

#define UTS1_RXEMPTY    (1<<5)

#define UTS1_TXFULL     (1<<4)

#define UTS1_RXFULL     (1<<3)



static void imx_update(IMXSerialState *s)

{

    uint32_t flags;
@@ -203,8 +125,10 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, 
            s->usr2 &= ~USR2_RDR;

            s->uts1 |= UTS1_RXEMPTY;

            imx_update(s);

            if (s->chr) {

                qemu_chr_accept_input(s->chr);

            }

        }

        return c;



    case 0x20: /* UCR1 */
@@ -242,7 +166,7 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, 
        return 0x0; /* TODO */



    default:

        IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset);

        IPRINTF("%s: bad offset: 0x%x\n", __func__, (int)offset);

        return 0;

    }

}
@@ -290,9 +214,11 @@ static void imx_serial_write(void *opaque, hwaddr offset, 
        }

        if (value & UCR2_RXEN) {

            if (!(s->ucr2 & UCR2_RXEN)) {

                if (s->chr) {

                    qemu_chr_accept_input(s->chr);

                }

            }

        }

        s->ucr2 = value & 0xffff;

        break;
@@ -344,7 +270,7 @@ static void imx_serial_write(void *opaque, hwaddr offset, 
        break;



    default:

        IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset);

        IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset);

    }

}
@@ -384,16 +310,10 @@ static const struct MemoryRegionOps imx_serial_ops = { 
    .endianness = DEVICE_NATIVE_ENDIAN,

};



static int imx_serial_init(SysBusDevice *dev)

static void imx_serial_realize(DeviceState *dev, Error **errp)

{

    IMXSerialState *s = IMX_SERIAL(dev);





    memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,

                          "imx-serial", 0x1000);

    sysbus_init_mmio(dev, &s->iomem);

    sysbus_init_irq(dev, &s->irq);



    if (s->chr) {

        qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,

                              imx_event, s);
@@ -401,8 +321,17 @@ static int imx_serial_init(SysBusDevice *dev) 
        DPRINTF("No char dev for uart at 0x%lx\n",

                (unsigned long)s->iomem.ram_addr);

    }

}



    return 0;

static void imx_serial_init(Object *obj)

{

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    IMXSerialState *s = IMX_SERIAL(obj);



    memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,

                          TYPE_IMX_SERIAL, 0x1000);

    sysbus_init_mmio(sbd, &s->iomem);

    sysbus_init_irq(sbd, &s->irq);

}



void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
@@ -439,7 +368,7 @@ void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq) 
}





static Property imx32_serial_properties[] = {

static Property imx_serial_properties[] = {

    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),

    DEFINE_PROP_END_OF_LIST(),

};
@@ -447,20 +376,20 @@ static Property imx32_serial_properties[] = { 
static void imx_serial_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);



    k->init = imx_serial_init;

    dc->realize = imx_serial_realize;

    dc->vmsd = &vmstate_imx_serial;

    dc->reset = imx_serial_reset_at_boot;

    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);

    dc->desc = "i.MX series UART";

    dc->props = imx32_serial_properties;

    dc->props = imx_serial_properties;

}



static const TypeInfo imx_serial_info = {

    .name           = TYPE_IMX_SERIAL,

    .parent         = TYPE_SYS_BUS_DEVICE,

    .instance_size  = sizeof(IMXSerialState),

    .instance_init  = imx_serial_init,

    .class_init     = imx_serial_class_init,

};

hw/cpu/a15mpcore.c

+16 −13
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 


#include "hw/cpu/a15mpcore.h"

#include "sysemu/kvm.h"

#include "kvm_arm.h"



static void a15mp_priv_set_irq(void *opaque, int irq, int level)

{
@@ -33,16 +34,11 @@ static void a15mp_priv_initfn(Object *obj) 
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    A15MPPrivState *s = A15MPCORE_PRIV(obj);

    DeviceState *gicdev;

    const char *gictype = "arm_gic";



    if (kvm_irqchip_in_kernel()) {

        gictype = "kvm-arm-gic";

    }



    memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);

    sysbus_init_mmio(sbd, &s->container);



    object_initialize(&s->gic, sizeof(s->gic), gictype);

    object_initialize(&s->gic, sizeof(s->gic), gic_class_name());

    gicdev = DEVICE(&s->gic);

    qdev_set_parent_bus(gicdev, sysbus_get_default());

    qdev_prop_set_uint32(gicdev, "revision", 2);
@@ -79,14 +75,21 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) 
    for (i = 0; i < s->num_cpu; i++) {

        DeviceState *cpudev = DEVICE(qemu_get_cpu(i));

        int ppibase = s->num_irq - 32 + i * 32;

        /* physical timer; we wire it up to the non-secure timer's ID,

         * since a real A15 always has TrustZone but QEMU doesn't.

        int irq;

        /* Mapping from the output timer irq lines from the CPU to the

         * GIC PPI inputs used on the A15:

         */

        qdev_connect_gpio_out(cpudev, 0,

                              qdev_get_gpio_in(gicdev, ppibase + 30));

        /* virtual timer */

        qdev_connect_gpio_out(cpudev, 1,

                              qdev_get_gpio_in(gicdev, ppibase + 27));

        const int timer_irq[] = {

            [GTIMER_PHYS] = 30,

            [GTIMER_VIRT] = 27,

            [GTIMER_HYP]  = 26,

            [GTIMER_SEC]  = 29,

        };

        for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {

            qdev_connect_gpio_out(cpudev, irq,

                                  qdev_get_gpio_in(gicdev,

                                                   ppibase + timer_irq[irq]));

        }

    }



    /* Memory map (addresses are offsets from PERIPHBASE):

hw/intc/arm_gic.c

+19 −45
Original line number Diff line number Diff line
@@ -922,12 +922,6 @@ static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 
    }

}



static const MemoryRegionOps gic_dist_ops = {

    .read_with_attrs = gic_dist_read,

    .write_with_attrs = gic_dist_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

};



static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,

                                uint64_t *data, MemTxAttrs attrs)

{
@@ -1056,10 +1050,17 @@ static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 
    return gic_cpu_write(s, id, addr, value, attrs);

}



static const MemoryRegionOps gic_thiscpu_ops = {

static const MemoryRegionOps gic_ops[2] = {

    {

        .read_with_attrs = gic_dist_read,

        .write_with_attrs = gic_dist_write,

        .endianness = DEVICE_NATIVE_ENDIAN,

    },

    {

        .read_with_attrs = gic_thiscpu_read,

        .write_with_attrs = gic_thiscpu_write,

        .endianness = DEVICE_NATIVE_ENDIAN,

    }

};



static const MemoryRegionOps gic_cpu_ops = {
@@ -1068,31 +1069,10 @@ static const MemoryRegionOps gic_cpu_ops = { 
    .endianness = DEVICE_NATIVE_ENDIAN,

};



/* This function is used by nvic model */

void gic_init_irqs_and_distributor(GICState *s)

{

    SysBusDevice *sbd = SYS_BUS_DEVICE(s);

    int i;



    i = s->num_irq - GIC_INTERNAL;

    /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.

     * GPIO array layout is thus:

     *  [0..N-1] SPIs

     *  [N..N+31] PPIs for CPU 0

     *  [N+32..N+63] PPIs for CPU 1

     *   ...

     */

    if (s->revision != REV_NVIC) {

        i += (GIC_INTERNAL * s->num_cpu);

    }

    qdev_init_gpio_in(DEVICE(s), gic_set_irq, i);

    for (i = 0; i < NUM_CPU(s); i++) {

        sysbus_init_irq(sbd, &s->parent_irq[i]);

    }

    for (i = 0; i < NUM_CPU(s); i++) {

        sysbus_init_irq(sbd, &s->parent_fiq[i]);

    }

    memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s,

                          "gic_dist", 0x1000);

    gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);

}



static void arm_gic_realize(DeviceState *dev, Error **errp)
@@ -1110,28 +1090,22 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) 
        return;

    }



    gic_init_irqs_and_distributor(s);

    /* This creates distributor and main CPU interface (s->cpuiomem[0]) */

    gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);



    /* Memory regions for the CPU interfaces (NVIC doesn't have these):

     * a region for "CPU interface for this core", then a region for

     * "CPU interface for core 0", "for core 1", ...

    /* Extra core-specific regions for the CPU interfaces. This is

     * necessary for "franken-GIC" implementations, for example on

     * Exynos 4.

     * NB that the memory region size of 0x100 applies for the 11MPCore

     * and also cores following the GIC v1 spec (ie A9).

     * GIC v2 defines a larger memory region (0x1000) so this will need

     * to be extended when we implement A15.

     */

    memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s,

                          "gic_cpu", 0x100);

    for (i = 0; i < NUM_CPU(s); i++) {

        s->backref[i] = s;

        memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,

                              &s->backref[i], "gic_cpu", 0x100);

    }

    /* Distributor */

    sysbus_init_mmio(sbd, &s->iomem);

    /* cpu interfaces (one for "current cpu" plus one per cpu) */

    for (i = 0; i <= NUM_CPU(s); i++) {

        sysbus_init_mmio(sbd, &s->cpuiomem[i]);

        sysbus_init_mmio(sbd, &s->cpuiomem[i+1]);

    }

}