Commit 40cd7180 authored by Yongbok Kim's avatar Yongbok Kim Committed by Aleksandar Markovic
Browse files

target/mips: Update ITU to handle bus errors 



Update ITU to handle bus errors.

Reviewed-by: default avatarStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: default avatarYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 043715d1

hw/misc/mips_itu.c

+22 −0
Original line number Diff line number Diff line
@@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c) 
    view_pv_common_write(c);

}



static void raise_exception(int excp)

{

    current_cpu->exception_index = excp;

    cpu_loop_exit(current_cpu);

}



static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)

{

    MIPSITUState *s = (MIPSITUState *)opaque;
@@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 
    ITCView view = get_itc_view(addr);

    uint64_t ret = -1;



    switch (size) {

    case 1:

    case 2:

        s->icr0 |= 1 << ITC_ICR0_ERR_AXI;

        raise_exception(EXCP_DBE);

        return 0;

    }



    switch (view) {

    case ITCVIEW_BYPASS:

        ret = view_bypass_read(cell);
@@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 
    ITCStorageCell *cell = get_cell(s, addr);

    ITCView view = get_itc_view(addr);



    switch (size) {

    case 1:

    case 2:

        s->icr0 |= 1 << ITC_ICR0_ERR_AXI;

        raise_exception(EXCP_DBE);

        return;

    }



    switch (view) {

    case ITCVIEW_BYPASS:

        view_bypass_write(cell, data);