Commit 40b2ccb1 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/arm: Move isa detection to tcg-target.h 



This allows us to use this detection within the TCG_TARGET_HAS_*
macros, instead of requiring a function call into tcg-target.inc.c.

Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent e2179f94

tcg/arm/tcg-target.h

+32 −4
Original line number Diff line number Diff line
@@ -26,6 +26,37 @@ 
#ifndef ARM_TCG_TARGET_H

#define ARM_TCG_TARGET_H



/* The __ARM_ARCH define is provided by gcc 4.8.  Construct it otherwise.  */

#ifndef __ARM_ARCH

# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \

     || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \

     || defined(__ARM_ARCH_7EM__)

#  define __ARM_ARCH 7

# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \

       || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \

       || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)

#  define __ARM_ARCH 6

# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \

       || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \

       || defined(__ARM_ARCH_5TEJ__)

#  define __ARM_ARCH 5

# else

#  define __ARM_ARCH 4

# endif

#endif



extern int arm_arch;



#if defined(__ARM_ARCH_5T__) \

    || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)

# define use_armv5t_instructions 1

#else

# define use_armv5t_instructions use_armv6_instructions

#endif



#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)

#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)



#undef TCG_TARGET_STACK_GROWSUP

#define TCG_TARGET_INSN_UNIT_SIZE 4

#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
@@ -79,7 +110,7 @@ extern bool use_idiv_instructions; 
#define TCG_TARGET_HAS_eqv_i32          0

#define TCG_TARGET_HAS_nand_i32         0

#define TCG_TARGET_HAS_nor_i32          0

#define TCG_TARGET_HAS_deposit_i32      1

#define TCG_TARGET_HAS_deposit_i32      use_armv7_instructions

#define TCG_TARGET_HAS_extract_i32      0

#define TCG_TARGET_HAS_sextract_i32     0

#define TCG_TARGET_HAS_movcond_i32      1
@@ -90,9 +121,6 @@ extern bool use_idiv_instructions; 
#define TCG_TARGET_HAS_div_i32          use_idiv_instructions

#define TCG_TARGET_HAS_rem_i32          0



extern bool tcg_target_deposit_valid(int ofs, int len);

#define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid



enum {

    TCG_AREG0 = TCG_REG_R6,

};

tcg/arm/tcg-target.inc.c

+1 −40
Original line number Diff line number Diff line
@@ -25,36 +25,7 @@ 
#include "elf.h"

#include "tcg-be-ldst.h"



/* The __ARM_ARCH define is provided by gcc 4.8.  Construct it otherwise.  */

#ifndef __ARM_ARCH

# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \

     || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \

     || defined(__ARM_ARCH_7EM__)

#  define __ARM_ARCH 7

# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \

       || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \

       || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)

#  define __ARM_ARCH 6

# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \

       || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \

       || defined(__ARM_ARCH_5TEJ__)

#  define __ARM_ARCH 5

# else

#  define __ARM_ARCH 4

# endif

#endif



static int arm_arch = __ARM_ARCH;



#if defined(__ARM_ARCH_5T__) \

    || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)

# define use_armv5t_instructions 1

#else

# define use_armv5t_instructions use_armv6_instructions

#endif



#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)

#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)

int arm_arch = __ARM_ARCH;



#ifndef use_idiv_instructions

bool use_idiv_instructions;
@@ -730,16 +701,6 @@ static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) 
    }

}



bool tcg_target_deposit_valid(int ofs, int len)

{

    /* ??? Without bfi, we could improve over generic code by combining

       the right-shift from a non-zero ofs with the orr.  We do run into

       problems when rd == rs, and the mask generated from ofs+len doesn't

       fit into an immediate.  We would have to be careful not to pessimize

       wrt the optimizations performed on the expanded code.  */

    return use_armv7_instructions;

}



static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd,

                                   TCGArg a1, int ofs, int len, bool const_a1)

{