Commit 406bc339 authored by Pranith Kumar's avatar Pranith Kumar Committed by Paolo Bonzini
Browse files

Revert "exec.c: Fix breakpoint invalidation race" 



Now that we have proper locking after MTTCG patches have landed, we
can revert the commit.  This reverts commit

a9353fe8.

CC: Peter Maydell <peter.maydell@linaro.org>
CC: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarPranith Kumar <bobby.prani@gmail.com>
Message-Id: <20170712215143.19594-1-bobby.prani@gmail.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 04bf2526

exec.c

+19 −6
Original line number Diff line number Diff line
@@ -775,15 +775,28 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) 
#endif

}



#if defined(CONFIG_USER_ONLY)

static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)

{

    /* Flush the whole TB as this will not have race conditions

     * even if we don't have proper locking yet.

     * Ideally we would just invalidate the TBs for the

     * specified PC.

     */

    tb_flush(cpu);

    mmap_lock();

    tb_lock();

    tb_invalidate_phys_page_range(pc, pc + 1, 0);

    tb_unlock();

    mmap_unlock();

}

#else

static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)

{

    MemTxAttrs attrs;

    hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);

    int asidx = cpu_asidx_from_attrs(cpu, attrs);

    if (phys != -1) {

        /* Locks grabbed by tb_invalidate_phys_addr */

        tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,

                                phys | (pc & ~TARGET_PAGE_MASK));

    }

}

#endif



#if defined(CONFIG_USER_ONLY)

void cpu_watchpoint_remove_all(CPUState *cpu, int mask)

include/exec/exec-all.h

+3 −0
Original line number Diff line number Diff line
@@ -290,6 +290,9 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 
                                                       uint16_t idxmap)

{

}

static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)

{

}

#endif



#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */