Commit 40612000 authored by Julian Brown's avatar Julian Brown Committed by Peter Maydell
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arm: Correctly handle watchpoints for BE32 CPUs 



In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers.  This patch reverses the address
adjustment before performing the comparison with the help of a new CPUClass
hook.

This version of the patch augments and tidies up comments a little.

Signed-off-by: default avatarJulian Brown <julian@codesourcery.com>
Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent f7478a92

exec.c

+1 −0
Original line number Diff line number Diff line
@@ -2115,6 +2115,7 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) 
        return;

    }

    vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;

    vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);

    QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {

        if (cpu_watchpoint_address_matches(wp, vaddr, len)

            && (wp->flags & flags)) {

include/qom/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -132,6 +132,8 @@ struct TranslationBlock; 
 * @cpu_exec_exit: Callback for cpu_exec cleanup.

 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.

 * @disas_set_info: Setup architecture specific components of disassembly info

 * @adjust_watchpoint_address: Perform a target-specific adjustment to an

 * address before attempting to match it against watchpoints.

 *

 * Represents a CPU family or model.

 */
@@ -195,6 +197,7 @@ typedef struct CPUClass { 
    bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);



    void (*disas_set_info)(CPUState *cpu, disassemble_info *info);

    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);

} CPUClass;



#ifdef HOST_WORDS_BIGENDIAN

qom/cpu.c

+6 −0
Original line number Diff line number Diff line
@@ -391,6 +391,11 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) 
    return cpu->cpu_index;

}



static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)

{

    return addr;

}



static void cpu_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);
@@ -415,6 +420,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) 
    k->cpu_exec_enter = cpu_common_noop;

    k->cpu_exec_exit = cpu_common_noop;

    k->cpu_exec_interrupt = cpu_common_exec_interrupt;

    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;

    set_bit(DEVICE_CATEGORY_CPU, dc->categories);

    dc->realize = cpu_common_realizefn;

    dc->unrealize = cpu_common_unrealizefn;

target/arm/cpu.c

+3 −0
Original line number Diff line number Diff line
@@ -1675,6 +1675,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) 
    cc->gdb_stop_before_watchpoint = true;

    cc->debug_excp_handler = arm_debug_excp_handler;

    cc->debug_check_watchpoint = arm_debug_check_watchpoint;

#if !defined(CONFIG_USER_ONLY)

    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;

#endif



    cc->disas_set_info = arm_disas_set_info;

}

target/arm/internals.h

+5 −0
Original line number Diff line number Diff line
@@ -444,6 +444,11 @@ void hw_breakpoint_update_all(ARMCPU *cpu); 
/* Callback function for checking if a watchpoint should trigger. */

bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);



/* Adjust addresses (in BE32 mode) before testing against watchpoint

 * addresses.

 */

vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);



/* Callback function for when a watchpoint or breakpoint triggers. */

void arm_debug_excp_handler(CPUState *cs);