Commit 403aacdb authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass 



and use the value to define precisely the default value of the LPCR in
the helper routine cpu_ppc_set_papr()

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 5d8424db

target/ppc/cpu-qom.h

+1 −0
Original line number Diff line number Diff line
@@ -191,6 +191,7 @@ typedef struct PowerPCCPUClass { 
    uint64_t insns_flags;

    uint64_t insns_flags2;

    uint64_t msr_mask;

    uint64_t lpcr_pm;           /* Power-saving mode Exit Cause Enable bits */

    powerpc_mmu_t   mmu_model;

    powerpc_excp_t  excp_model;

    powerpc_input_t bus_model;

target/ppc/translate_init.c

+11 −12
Original line number Diff line number Diff line
@@ -8535,6 +8535,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 
    pcc->l1_dcache_size = 0x8000;

    pcc->l1_icache_size = 0x8000;

    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;

    pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;

}



static void init_proc_POWER8(CPUPPCState *env)
@@ -8704,6 +8705,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 
    pcc->l1_dcache_size = 0x8000;

    pcc->l1_icache_size = 0x8000;

    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;

    pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |

                   LPCR_P8_PECE3 | LPCR_P8_PECE4;

}



#ifdef CONFIG_SOFTMMU
@@ -8898,11 +8901,13 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 
    pcc->l1_dcache_size = 0x8000;

    pcc->l1_icache_size = 0x8000;

    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;

    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;

}



#if !defined(CONFIG_USER_ONLY)

void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)

{

    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);

    CPUPPCState *env = &cpu->env;

    ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];

    ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
@@ -8932,8 +8937,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 
    lpcr->default_value &= ~LPCR_RMLS;

    lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;



    switch (env->mmu_model) {

    case POWERPC_MMU_3_00:

    if (env->mmu_model == POWERPC_MMU_3_00) {

        /* By default we choose legacy mode and switch to new hash or radix

         * when a register process table hcall is made. So disable process

         * tables and guest translation shootdown by default
@@ -8947,18 +8951,13 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 
        } else {

            lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);

        }

        lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |

                               LPCR_OEE;

        break;

    default:

        /* P7 and P8 has slightly different PECE bits, mostly because P8 adds

         * bit 47 and 48 which are reserved on P7. Here we set them all, which

         * will work as expected for both implementations

         */

        lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |

                               LPCR_P8_PECE3 | LPCR_P8_PECE4;

    }



    /* Also set the power-saving mode bits which depend on the CPU

     * family

     */

    lpcr->default_value |= pcc->lpcr_pm;



    /* We should be followed by a CPU reset but update the active value

     * just in case...

     */