Commit 3f68b8a5 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Change the type of vfp.regs 



All direct users of this field want an integral value.  Drop all
of the extra casting between uint64_t and float64.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180119045438.28582-6-richard.henderson@linaro.org
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent e7c06c4e

target/arm/arch_dump.c

+2 −2
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, 
    aarch64_note_init(&note, s, "CORE", 5, NT_PRFPREG, sizeof(note.vfp));



    for (i = 0; i < 64; ++i) {

        note.vfp.vregs[i] = cpu_to_dump64(s, float64_val(env->vfp.regs[i]));

        note.vfp.vregs[i] = cpu_to_dump64(s, env->vfp.regs[i]);

    }



    if (s->dump_info.d_endian == ELFDATA2MSB) {
@@ -229,7 +229,7 @@ static int arm_write_elf32_vfp(WriteCoreDumpFunction f, CPUARMState *env, 
    arm_note_init(&note, s, "LINUX", 6, NT_ARM_VFP, sizeof(note.vfp));



    for (i = 0; i < 32; ++i) {

        note.vfp.vregs[i] = cpu_to_dump64(s, float64_val(env->vfp.regs[i]));

        note.vfp.vregs[i] = cpu_to_dump64(s, env->vfp.regs[i]);

    }



    note.vfp.fpscr = cpu_to_dump32(s, vfp_get_fpscr(env));

target/arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -492,7 +492,7 @@ typedef struct CPUARMState { 
         * the two execution states, and means we do not need to explicitly

         * map these registers when changing states.

         */

        float64 regs[64];

        uint64_t regs[64];



        uint32_t xregs[16];

        /* We store these fpcsr fields separately for convenience.  */

target/arm/helper.c

+10 −10
Original line number Diff line number Diff line
@@ -64,15 +64,15 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 
    /* VFP data registers are always little-endian.  */

    nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;

    if (reg < nregs) {

        stfq_le_p(buf, env->vfp.regs[reg]);

        stq_le_p(buf, env->vfp.regs[reg]);

        return 8;

    }

    if (arm_feature(env, ARM_FEATURE_NEON)) {

        /* Aliases for Q regs.  */

        nregs += 16;

        if (reg < nregs) {

            stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);

            stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);

            stq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);

            stq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);

            return 16;

        }

    }
@@ -90,14 +90,14 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 


    nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;

    if (reg < nregs) {

        env->vfp.regs[reg] = ldfq_le_p(buf);

        env->vfp.regs[reg] = ldq_le_p(buf);

        return 8;

    }

    if (arm_feature(env, ARM_FEATURE_NEON)) {

        nregs += 16;

        if (reg < nregs) {

            env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);

            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);

            env->vfp.regs[(reg - 32) * 2] = ldq_le_p(buf);

            env->vfp.regs[(reg - 32) * 2 + 1] = ldq_le_p(buf + 8);

            return 16;

        }

    }
@@ -114,8 +114,8 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 
    switch (reg) {

    case 0 ... 31:

        /* 128 bit FP register */

        stfq_le_p(buf, env->vfp.regs[reg * 2]);

        stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);

        stq_le_p(buf, env->vfp.regs[reg * 2]);

        stq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);

        return 16;

    case 32:

        /* FPSR */
@@ -135,8 +135,8 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 
    switch (reg) {

    case 0 ... 31:

        /* 128 bit FP register */

        env->vfp.regs[reg * 2] = ldfq_le_p(buf);

        env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);

        env->vfp.regs[reg * 2] = ldq_le_p(buf);

        env->vfp.regs[reg * 2 + 1] = ldq_le_p(buf + 8);

        return 16;

    case 32:

        /* FPSR */

target/arm/machine.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ static const VMStateDescription vmstate_vfp = { 
    .minimum_version_id = 3,

    .needed = vfp_needed,

    .fields = (VMStateField[]) {

        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),

        VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64),

        /* The xregs array is a little awkward because element 1 (FPSCR)

         * requires a specific accessor, so we have to split it up in

         * the vmstate:

target/arm/translate-a64.c

+4 −4
Original line number Diff line number Diff line
@@ -165,12 +165,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, 
    if (flags & CPU_DUMP_FPU) {

        int numvfpregs = 32;

        for (i = 0; i < numvfpregs; i += 2) {

            uint64_t vlo = float64_val(env->vfp.regs[i * 2]);

            uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);

            uint64_t vlo = env->vfp.regs[i * 2];

            uint64_t vhi = env->vfp.regs[(i * 2) + 1];

            cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",

                        i, vhi, vlo);

            vlo = float64_val(env->vfp.regs[(i + 1) * 2]);

            vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);

            vlo = env->vfp.regs[(i + 1) * 2];

            vhi = env->vfp.regs[((i + 1) * 2) + 1];

            cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",

                        i + 1, vhi, vlo);

        }