Commit 3ef521ee authored by Aleksandar Markovic's avatar Aleksandar Markovic
Browse files

target/mips: Add CP0 register MemoryMapID 



Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.

Reviewed-by: default avatarAleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 04992c8c

target/mips/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -536,6 +536,7 @@ struct CPUMIPSState { 
 */

    target_ulong CP0_Context;

    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];

    int32_t CP0_MemoryMapID;

/*

 * CP0 Register 5

 */

target/mips/machine.c

+3 −2
Original line number Diff line number Diff line
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = { 


const VMStateDescription vmstate_mips_cpu = {

    .name = "cpu",

    .version_id = 16,

    .minimum_version_id = 16,

    .version_id = 17,

    .minimum_version_id = 17,

    .post_load = cpu_post_load,

    .fields = (VMStateField[]) {

        /* Active TC */
@@ -253,6 +253,7 @@ const VMStateDescription vmstate_mips_cpu = { 
        VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),

        VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),

        VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),

        VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),

        VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),