Commit 3de79d33 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Fix Cortex-R5F MVFR values 



The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 06db8196

target/arm/cpu.c

+2 −0
Original line number Diff line number Diff line
@@ -1609,6 +1609,8 @@ static void cortex_r5f_initfn(Object *obj) 


    cortex_r5_initfn(obj);

    set_feature(&cpu->env, ARM_FEATURE_VFP3);

    cpu->isar.mvfr0 = 0x10110221;

    cpu->isar.mvfr1 = 0x00000011;

}



static const ARMCPRegInfo cortexa8_cp_reginfo[] = {