Commit 3ddf0b5c authored by Thiemo Seufer's avatar Thiemo Seufer
Browse files

Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
parent c92843b5

target-mips/helper.c

+6 −3
Original line number Diff line number Diff line
@@ -369,6 +369,7 @@ void do_interrupt (CPUState *env) 
        }

    enter_debug_mode:

        env->hflags |= MIPS_HFLAG_DM;

        if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))

            env->hflags |= MIPS_HFLAG_64;

        env->hflags &= ~MIPS_HFLAG_UM;

        /* EJTAG probe trap enable is not implemented... */
@@ -395,6 +396,7 @@ void do_interrupt (CPUState *env) 
            env->CP0_ErrorEPC = env->PC;

        }

        env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);

        if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))

            env->hflags |= MIPS_HFLAG_64;

        env->hflags &= ~MIPS_HFLAG_UM;

        if (!(env->CP0_Status & (1 << CP0St_EXL)))
@@ -494,6 +496,7 @@ void do_interrupt (CPUState *env) 
                env->CP0_Cause &= ~(1 << CP0Ca_BD);

            }

            env->CP0_Status |= (1 << CP0St_EXL);

            if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))

                env->hflags |= MIPS_HFLAG_64;

            env->hflags &= ~MIPS_HFLAG_UM;

        }

target-mips/op.c

+9 −6
Original line number Diff line number Diff line
@@ -1358,9 +1358,10 @@ void op_mtc0_status (void) 
        (val & (1 << CP0St_UM)))

        env->hflags |= MIPS_HFLAG_UM;

#ifdef TARGET_MIPS64

    if ((env->hflags & MIPS_HFLAG_UM) &&

    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||

        ((env->hflags & MIPS_HFLAG_UM) &&

        !(val & (1 << CP0St_PX)) &&

        !(val & (1 << CP0St_UX)))

        !(val & (1 << CP0St_UX))))

        env->hflags &= ~MIPS_HFLAG_64;

#endif

    if (val & (1 << CP0St_CU1))
@@ -2318,9 +2319,10 @@ void op_eret (void) 
        (env->CP0_Status & (1 << CP0St_UM)))

        env->hflags |= MIPS_HFLAG_UM;

#ifdef TARGET_MIPS64

    if ((env->hflags & MIPS_HFLAG_UM) &&

    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||

        ((env->hflags & MIPS_HFLAG_UM) &&

        !(env->CP0_Status & (1 << CP0St_PX)) &&

        !(env->CP0_Status & (1 << CP0St_UX)))

        !(env->CP0_Status & (1 << CP0St_UX))))

        env->hflags &= ~MIPS_HFLAG_64;

#endif

    if (loglevel & CPU_LOG_EXEC)
@@ -2341,9 +2343,10 @@ void op_deret (void) 
        (env->CP0_Status & (1 << CP0St_UM)))

        env->hflags |= MIPS_HFLAG_UM;

#ifdef TARGET_MIPS64

    if ((env->hflags & MIPS_HFLAG_UM) &&

    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||

        ((env->hflags & MIPS_HFLAG_UM) &&

        !(env->CP0_Status & (1 << CP0St_PX)) &&

        !(env->CP0_Status & (1 << CP0St_UX)))

        !(env->CP0_Status & (1 << CP0St_UX))))

        env->hflags &= ~MIPS_HFLAG_64;

#endif

    if (loglevel & CPU_LOG_EXEC)

target-mips/translate.c

+8 −8
Original line number Diff line number Diff line
@@ -2225,6 +2225,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 
        switch (sel) {

        case 0:

#ifdef TARGET_MIPS64

	    if (!(ctx->hflags & MIPS_HFLAG_64))

	        goto die;

            gen_op_mfc0_xcontext();

            rn = "XContext";

            break;
@@ -2781,6 +2783,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 
        switch (sel) {

        case 0:

#ifdef TARGET_MIPS64

	    if (!(ctx->hflags & MIPS_HFLAG_64))

	        goto die;

            gen_op_mtc0_xcontext();

            rn = "XContext";

            break;
@@ -3331,11 +3335,9 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 
    case 20:

        switch (sel) {

        case 0:

#ifdef TARGET_MIPS64

            gen_op_dmfc0_xcontext();

            rn = "XContext";

            break;

#endif

        default:

            goto die;

        }
@@ -3878,11 +3880,9 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 
    case 20:

        switch (sel) {

        case 0:

#ifdef TARGET_MIPS64

            gen_op_mtc0_xcontext();

            rn = "XContext";

            break;

#endif

        default:

            goto die;

        }
@@ -4107,6 +4107,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int 
        break;

#ifdef TARGET_MIPS64

    case OPC_DMFC0:

        if (!(ctx->hflags & MIPS_HFLAG_64))

            generate_exception(ctx, EXCP_RI);

        if (rt == 0) {

            /* Treat as NOP */

            return;
@@ -4116,6 +4118,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int 
        opn = "dmfc0";

        break;

    case OPC_DMTC0:

        if (!(ctx->hflags & MIPS_HFLAG_64))

            generate_exception(ctx, EXCP_RI);

        GEN_LOAD_REG_TN(T0, rt);

        gen_dmtc0(env,ctx, rd, ctx->opcode & 0x7);

        opn = "dmtc0";
@@ -6183,11 +6187,7 @@ void cpu_reset (CPUMIPSState *env) 
    } else {

        env->CP0_ErrorEPC = env->PC;

    }

#ifdef TARGET_MIPS64

    env->hflags = MIPS_HFLAG_64;

#else

    env->hflags = 0;

#endif

    env->PC = (int32_t)0xBFC00000;

    env->CP0_Wired = 0;

    /* SMP not implemented */

target-mips/translate_init.c

+9 −7
Original line number Diff line number Diff line
@@ -86,7 +86,6 @@ static mips_def_t mips_defs[] = 
        .SYNCI_Step = 32,

        .CCRes = 2,

        .Status_rw_bitmask = 0x3278FF17,

        .SEGBITS = 32,

    },

    {

        .name = "4KEcR1",
@@ -100,7 +99,6 @@ static mips_def_t mips_defs[] = 
        .SYNCI_Step = 32,

        .CCRes = 2,

        .Status_rw_bitmask = 0x3278FF17,

        .SEGBITS = 32,

    },

    {

        .name = "4KEc",
@@ -114,7 +112,6 @@ static mips_def_t mips_defs[] = 
        .SYNCI_Step = 32,

        .CCRes = 2,

        .Status_rw_bitmask = 0x3278FF17,

        .SEGBITS = 32,

    },

    {

        .name = "24Kc",
@@ -128,7 +125,6 @@ static mips_def_t mips_defs[] = 
        .SYNCI_Step = 32,

        .CCRes = 2,

        .Status_rw_bitmask = 0x3278FF17,

        .SEGBITS = 32,

    },

    {

        .name = "24Kf",
@@ -144,7 +140,6 @@ static mips_def_t mips_defs[] = 
        .Status_rw_bitmask = 0x3678FF17,

        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |

                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),

        .SEGBITS = 32,

    },

#ifdef TARGET_MIPS64

    {
@@ -293,8 +288,15 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) 
    env->Status_rw_bitmask = def->Status_rw_bitmask;

    env->fcr0 = def->CP1_fcr0;

#ifdef TARGET_MIPS64

    if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))

    {

        env->hflags |= MIPS_HFLAG_64;

        env->SEGBITS = def->SEGBITS;

        env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);

    } else {

        env->SEGBITS = 32;

        env->SEGMask = 0xFFFFFFFF;

    }

#endif

#ifdef CONFIG_USER_ONLY

    if (env->CP0_Config1 & (1 << CP0C1_FP))