Commit 3dc91ddb authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Move id_aa64mmfr* to ARMISARegisters 



At the same time, define the fields for these registers,
and use those defines in arm_pamax().

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-2-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
[PMM: fixed up typo (s/achf/ahcf/) belatedly spotted by RTH]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent f6ef171d

target/arm/cpu.h

+24 −2
Original line number Diff line number Diff line
@@ -818,6 +818,8 @@ struct ARMCPU { 
        uint64_t id_aa64isar1;

        uint64_t id_aa64pfr0;

        uint64_t id_aa64pfr1;

        uint64_t id_aa64mmfr0;

        uint64_t id_aa64mmfr1;

    } isar;

    uint32_t midr;

    uint32_t revidr;
@@ -839,8 +841,6 @@ struct ARMCPU { 
    uint64_t id_aa64dfr1;

    uint64_t id_aa64afr0;

    uint64_t id_aa64afr1;

    uint64_t id_aa64mmfr0;

    uint64_t id_aa64mmfr1;

    uint32_t dbgdidr;

    uint32_t clidr;

    uint64_t mp_affinity; /* MP ID without feature bits */
@@ -1557,6 +1557,28 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) 
FIELD(ID_AA64PFR0, RAS, 28, 4)

FIELD(ID_AA64PFR0, SVE, 32, 4)



FIELD(ID_AA64MMFR0, PARANGE, 0, 4)

FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)

FIELD(ID_AA64MMFR0, BIGEND, 8, 4)

FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)

FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)

FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)

FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)

FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)

FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)

FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)

FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)

FIELD(ID_AA64MMFR0, EXS, 44, 4)



FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)

FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)

FIELD(ID_AA64MMFR1, VH, 8, 4)

FIELD(ID_AA64MMFR1, HPDS, 12, 4)

FIELD(ID_AA64MMFR1, LO, 16, 4)

FIELD(ID_AA64MMFR1, PAN, 20, 4)

FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)

FIELD(ID_AA64MMFR1, XNX, 28, 4)



QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);



/* If adding a feature bit which corresponds to a Linux ELF

target/arm/cpu64.c

+3 −3
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ static void aarch64_a57_initfn(Object *obj) 
    cpu->pmceid0 = 0x00000000;

    cpu->pmceid1 = 0x00000000;

    cpu->isar.id_aa64isar0 = 0x00011120;

    cpu->id_aa64mmfr0 = 0x00001124;

    cpu->isar.id_aa64mmfr0 = 0x00001124;

    cpu->dbgdidr = 0x3516d000;

    cpu->clidr = 0x0a200023;

    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
@@ -195,7 +195,7 @@ static void aarch64_a53_initfn(Object *obj) 
    cpu->isar.id_aa64pfr0 = 0x00002222;

    cpu->id_aa64dfr0 = 0x10305106;

    cpu->isar.id_aa64isar0 = 0x00011120;

    cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */

    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */

    cpu->dbgdidr = 0x3516d000;

    cpu->clidr = 0x0a200023;

    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
@@ -249,7 +249,7 @@ static void aarch64_a72_initfn(Object *obj) 
    cpu->pmceid0 = 0x00000000;

    cpu->pmceid1 = 0x00000000;

    cpu->isar.id_aa64isar0 = 0x00011120;

    cpu->id_aa64mmfr0 = 0x00001124;

    cpu->isar.id_aa64mmfr0 = 0x00001124;

    cpu->dbgdidr = 0x3516d000;

    cpu->clidr = 0x0a200023;

    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */

target/arm/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -5207,11 +5207,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
            { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,

              .access = PL1_R, .type = ARM_CP_CONST,

              .resetvalue = cpu->id_aa64mmfr0 },

              .resetvalue = cpu->isar.id_aa64mmfr0 },

            { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST,

              .resetvalue = cpu->id_aa64mmfr1 },

              .resetvalue = cpu->isar.id_aa64mmfr1 },

            { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,

              .access = PL1_R, .type = ARM_CP_CONST,

target/arm/internals.h

+2 −1
Original line number Diff line number Diff line
@@ -229,7 +229,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) 
        [4] = 44,

        [5] = 48,

    };

    unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);

    unsigned int parange =

        FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);



    /* id_aa64mmfr0 is a read-only register so values outside of the

     * supported mappings can be considered an implementation error.  */

target/arm/kvm64.c

+4 −0
Original line number Diff line number Diff line
@@ -538,6 +538,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 
                              ARM64_SYS_REG(3, 0, 0, 6, 0));

        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,

                              ARM64_SYS_REG(3, 0, 0, 6, 1));

        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,

                              ARM64_SYS_REG(3, 0, 0, 7, 0));

        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,

                              ARM64_SYS_REG(3, 0, 0, 7, 1));



        /*

         * Note that if AArch32 support is not present in the host,