Loading target/sparc/translate.c +25 −2 Original line number Diff line number Diff line Loading @@ -2448,8 +2448,31 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) gen_ldstub(dc, dst, addr, da.mem_idx); break; default: /* ??? Should be DAE_invalid_asi. */ gen_exception(dc, TT_DATA_ACCESS); /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ if (parallel_cpus) { gen_helper_exit_atomic(cpu_env); } else { TCGv_i32 r_asi = tcg_const_i32(da.asi); TCGv_i32 r_mop = tcg_const_i32(MO_UB); TCGv_i64 s64, t64; save_state(dc); t64 = tcg_temp_new_i64(); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); s64 = tcg_const_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); tcg_temp_free_i64(s64); tcg_temp_free_i32(r_mop); tcg_temp_free_i32(r_asi); tcg_gen_trunc_i64_tl(dst, t64); tcg_temp_free_i64(t64); /* End the TB. */ dc->npc = DYNAMIC_PC; } break; } } Loading Loading
target/sparc/translate.c +25 −2 Original line number Diff line number Diff line Loading @@ -2448,8 +2448,31 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) gen_ldstub(dc, dst, addr, da.mem_idx); break; default: /* ??? Should be DAE_invalid_asi. */ gen_exception(dc, TT_DATA_ACCESS); /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ if (parallel_cpus) { gen_helper_exit_atomic(cpu_env); } else { TCGv_i32 r_asi = tcg_const_i32(da.asi); TCGv_i32 r_mop = tcg_const_i32(MO_UB); TCGv_i64 s64, t64; save_state(dc); t64 = tcg_temp_new_i64(); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); s64 = tcg_const_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); tcg_temp_free_i64(s64); tcg_temp_free_i32(r_mop); tcg_temp_free_i32(r_asi); tcg_gen_trunc_i64_tl(dst, t64); tcg_temp_free_i64(t64); /* End the TB. */ dc->npc = DYNAMIC_PC; } break; } } Loading