Commit 3d7f5721 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into staging 

* pmaydell/arm-devs.for-upstream: (22 commits)
  hw/pl031: Actually raise interrupt on timer expiry
  MAINTAINERS: Add hw/highbank.c maintainer
  Remove unnecessary includes of primecell.h
  hw/primecell.h: Remove obsolete pl080_init() declaration
  hw/arm_sysctl: Drop legacy init function
  hw/vexpress.c: Add vexpress-a15 machine
  arm_boot: Pass base address of GIC CPU interface, not whole GIC
  hw/vexpress.c: Instantiate the motherboard CLCD
  hw/vexpress.c: Factor out daughterboard-specific initialization
  hw/vexpress.c: Move secondary CPU boot code to SRAM
  hw/vexpress.c: Make motherboard peripheral memory map table-driven
  hw/a15mpcore.c: Add Cortex-A15 private peripheral model
  MAINTAINERS: Add maintainers for Exynos SOC.
  Exynos4210: added display controller implementation
  hw/exynos4210.c: Add LAN support for SMDKC210.
  hw/lan9118: Add basic 16-bit mode support.
  ARM: exynos4210: MCT support.
  ARM: exynos4210: basic Power Management Unit implementation
  ARM: exynos4210: PWM support.
  ARM: exynos4210: UART support
  ...
parents a19255a3 13a16f1d

MAINTAINERS

+14 −0
Original line number Diff line number Diff line
@@ -183,6 +183,20 @@ F: *win32* 


ARM Machines

------------

Exynos

M: Evgeny Voevodin <e.voevodin@samsung.com>

M: Maksim Kozlov <m.kozlov@samsung.com>

M: Igor Mitsyanko <i.mitsyanko@samsung.com>

M: Dmitry Solodkiy <d.solodkiy@samsung.com>

S: Maintained

F: hw/exynos*



Calxeda Highbank

M: Mark Langsdorf <mark.langsdorf@calxeda.com>

S: Supported

F: hw/highbank.c

F: hw/xgmac.c



Gumstix

M: qemu-devel@nongnu.org

S: Orphan

Makefile.target

+4 −1
Original line number Diff line number Diff line
@@ -344,8 +344,11 @@ obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o 
obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o

obj-arm-y += versatile_pci.o

obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o

obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o

obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o

obj-arm-y += exynos4210_pmu.o exynos4210_mct.o exynos4210_fimd.o

obj-arm-y += arm_l2x0.o

obj-arm-y += arm_mptimer.o

obj-arm-y += arm_mptimer.o a15mpcore.o

obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o

obj-arm-y += highbank.o

obj-arm-y += pl061.o

hw/a15mpcore.c

0 → 100644
+103 −0
Original line number Diff line number Diff line 
/*

 * Cortex-A15MPCore internal peripheral emulation.

 *

 * Copyright (c) 2012 Linaro Limited.

 * Written by Peter Maydell.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License along

 * with this program; if not, see <http://www.gnu.org/licenses/>.

 */



#include "sysbus.h"



/* Configuration for arm_gic.c:

 * max number of CPUs, how to ID current CPU

 */

#define NCPU 4



static inline int gic_get_current_cpu(void)

{

  return cpu_single_env->cpu_index;

}



#include "arm_gic.c"



/* A15MP private memory region.  */



typedef struct A15MPPrivState {

    gic_state gic;

    uint32_t num_cpu;

    uint32_t num_irq;

    MemoryRegion container;

} A15MPPrivState;



static int a15mp_priv_init(SysBusDevice *dev)

{

    A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);



    if (s->num_cpu > NCPU) {

        hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU);

    }



    gic_init(&s->gic, s->num_cpu, s->num_irq);



    /* Memory map (addresses are offsets from PERIPHBASE):

     *  0x0000-0x0fff -- reserved

     *  0x1000-0x1fff -- GIC Distributor

     *  0x2000-0x2fff -- GIC CPU interface

     *  0x4000-0x4fff -- GIC virtual interface control (not modelled)

     *  0x5000-0x5fff -- GIC virtual interface control (not modelled)

     *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)

     */

    memory_region_init(&s->container, "a15mp-priv-container", 0x8000);

    memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);

    memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]);



    sysbus_init_mmio(dev, &s->container);

    return 0;

}



static Property a15mp_priv_properties[] = {

    DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),

    /* The Cortex-A15MP may have anything from 0 to 224 external interrupt

     * IRQ lines (with another 32 internal). We default to 64+32, which

     * is the number provided by the Cortex-A15MP test chip in the

     * Versatile Express A15 development board.

     * Other boards may differ and should set this property appropriately.

     */

    DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96),

    DEFINE_PROP_END_OF_LIST(),

};



static void a15mp_priv_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = a15mp_priv_init;

    dc->props = a15mp_priv_properties;

    /* We currently have no savable state outside the common GIC state */

}



static TypeInfo a15mp_priv_info = {

    .name  = "a15mpcore_priv",

    .parent = TYPE_SYS_BUS_DEVICE,

    .instance_size  = sizeof(A15MPPrivState),

    .class_init = a15mp_priv_class_init,

};



static void a15mp_register_types(void)

{

    type_register_static(&a15mp_priv_info);

}



type_init(a15mp_register_types)

hw/arm-misc.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ struct arm_boot_info { 
     */

    target_phys_addr_t smp_loader_start;

    target_phys_addr_t smp_bootreg_addr;

    target_phys_addr_t smp_priv_base;

    target_phys_addr_t gic_cpu_if_addr;

    int nb_cpus;

    int board_id;

    int (*atag_board)(const struct arm_boot_info *info, void *p);

hw/arm_boot.c

+4 −4
Original line number Diff line number Diff line
@@ -43,16 +43,16 @@ static uint32_t bootloader[] = { 
 * location for the kernel secondary CPU entry point.

 */

static uint32_t smpboot[] = {

  0xe59f201c, /* ldr r2, privbase */

  0xe59f201c, /* ldr r2, gic_cpu_if */

  0xe59f001c, /* ldr r0, startaddr */

  0xe3a01001, /* mov r1, #1 */

  0xe5821100, /* str r1, [r2, #256] */

  0xe5821000, /* str r1, [r2] */

  0xe320f003, /* wfi */

  0xe5901000, /* ldr     r1, [r0] */

  0xe1110001, /* tst     r1, r1 */

  0x0afffffb, /* beq     <wfi> */

  0xe12fff11, /* bx      r1 */

  0,          /* privbase: Private memory region base address.  */

  0,          /* gic_cpu_if: base address of GIC CPU interface */

  0           /* bootreg: Boot register address is held here */

};
@@ -61,7 +61,7 @@ static void default_write_secondary(CPUState *env, 
{

    int n;

    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;

    smpboot[ARRAY_SIZE(smpboot) - 2] = info->smp_priv_base;

    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;

    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {

        smpboot[n] = tswap32(smpboot[n]);

    }