Commit 3c3efcf7 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Fill in ARMISARegisters for kvm32 



Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b653c55f

target/arm/kvm32.c

+35 −5
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 
     * and then query that CPU for the relevant ID registers.

     */

    int err = 0, fdarray[3];

    uint32_t midr, id_pfr0, mvfr1;

    uint32_t midr, id_pfr0;

    uint64_t features = 0;



    /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -71,9 +71,39 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 


    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));

    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));

    err |= read_sys_reg32(fdarray[2], &mvfr1,



    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,

                          ARM_CP15_REG32(0, 0, 2, 0));

    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,

                          ARM_CP15_REG32(0, 0, 2, 1));

    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,

                          ARM_CP15_REG32(0, 0, 2, 2));

    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,

                          ARM_CP15_REG32(0, 0, 2, 3));

    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,

                          ARM_CP15_REG32(0, 0, 2, 4));

    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,

                          ARM_CP15_REG32(0, 0, 2, 5));

    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,

                       ARM_CP15_REG32(0, 0, 2, 7))) {

        /*

         * Older kernels don't support reading ID_ISAR6. This register was

         * only introduced in ARMv8, so we can assume that it is zero on a

         * CPU that a kernel this old is running on.

         */

        ahcf->isar.id_isar6 = 0;

    }



    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,

                          KVM_REG_ARM | KVM_REG_SIZE_U32 |

                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);

    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,

                          KVM_REG_ARM | KVM_REG_SIZE_U32 |

                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);

    /*

     * FIXME: There is not yet a way to read MVFR2.

     * Fortunately there is not yet anything in there that affects migration.

     */



    kvm_arm_destroy_scratch_host_vcpu(fdarray);
@@ -95,13 +125,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 
    if (extract32(id_pfr0, 12, 4) == 1) {

        set_feature(&features, ARM_FEATURE_THUMB2EE);

    }

    if (extract32(mvfr1, 20, 4) == 1) {

    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {

        set_feature(&features, ARM_FEATURE_VFP_FP16);

    }

    if (extract32(mvfr1, 12, 4) == 1) {

    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {

        set_feature(&features, ARM_FEATURE_NEON);

    }

    if (extract32(mvfr1, 28, 4) == 1) {

    if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {

        /* FMAC support implies VFPv4 */

        set_feature(&features, ARM_FEATURE_VFP4);

    }