Commit 3c39c800 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/s390x: Finish implementing ETF2-ENH 



Missed the proper alignment in TRTO/TRTT, and ignoring the M3
field for all TRXX insns without ETF2-ENH.

Reviewed-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent afa26f3b

target/s390x/mem_helper.c

+10 −1
Original line number Diff line number Diff line
@@ -1265,13 +1265,22 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2, 
    uintptr_t ra = GETPC();

    int dsize = (sizes & 1) ? 1 : 2;

    int ssize = (sizes & 2) ? 1 : 2;

    uint64_t tbl = get_address(env, 1) & ~7;

    uint64_t tbl = get_address(env, 1);

    uint64_t dst = get_address(env, r1);

    uint64_t len = get_length(env, r1 + 1);

    uint64_t src = get_address(env, r2);

    uint32_t cc = 3;

    int i;



    /* The lower address bits of TBL are ignored.  For TROO, TROT, it's

       the low 3 bits (double-word aligned).  For TRTO, TRTT, it's either

       the low 12 bits (4K, without ETF2-ENH) or 3 bits (with ETF2-ENH).  */

    if (ssize == 2 && !s390_has_feat(S390_FEAT_ETF2_ENH)) {

        tbl &= -4096;

    } else {

        tbl &= -8;

    }



    check_alignment(env, len, ssize, ra);



    /* Lest we fail to service interrupts in a timely manner, */

target/s390x/translate.c

+3 −2
Original line number Diff line number Diff line
@@ -4356,8 +4356,9 @@ static ExitStatus op_trXX(DisasContext *s, DisasOps *o) 
    TCGv_i32 tst = tcg_temp_new_i32();

    int m3 = get_field(s->fields, m3);



    /* XXX: the C bit in M3 should be considered as 0 when the

       ETF2-enhancement facility is not installed.  */

    if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {

        m3 = 0;

    }

    if (m3 & 1) {

        tcg_gen_movi_i32(tst, -1);

    } else {