+85
−5
Loading
This implements the following Statistic registers (various counters) according to Intel's specs: TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUC ROC BPTC MPTC PTC... PRC... PLEASE NOTE: these registers will not be active, nor will migrate, until a compatibility flag will be set (in the next patch in this series). Signed-off-by:Leonid Bloch <leonid.bloch@ravellosystems.com> Signed-off-by:
Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by:
Jason Wang <jasowang@redhat.com>