Commit 3aca12f8 authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170127' into staging 



target-arm queue:
 * various minor M profile bugfixes
 * aspeed/smc: handle dummy bytes when doing fast reads in command mode
 * pflash_cfi01: fix per-device sector length in CFI table
 * arm: stellaris: make MII accesses complete immediately
 * hw/char/exynos4210_uart: Drop unused local variable frame_size
 * arm_gicv3: Fix broken logic in ELRSR calculation
 * dma: omap: check dma channel data_type

# gpg: Signature made Fri 27 Jan 2017 15:29:39 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170127: (22 commits)
  dma: omap: check dma channel data_type
  arm_gicv3: Fix broken logic in ELRSR calculation
  hw/char/exynos4210_uart: Drop unused local variable frame_size
  arm: stellaris: make MII accesses complete immediately
  armv7m: R14 should reset to 0xffffffff
  armv7m: FAULTMASK should be 0 on reset
  armv7m: Honour CCR.USERSETMPEND
  armv7m: Report no-coprocessor faults correctly
  armv7m: set CFSR.UNDEFINSTR on undefined instructions
  armv7m: honour CCR.STACKALIGN on exception entry
  armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR
  armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
  armv7m_nvic: keep a pointer to the CPU
  target/arm: Drop IS_M() macro
  pflash_cfi01: fix per-device sector length in CFI table
  armv7m: Clear FAULTMASK on return from non-NMI exceptions
  armv7m: Fix reads of CONTROL register bit 1
  hw/registerfields.h: Pull FIELD etc macros out of hw/register.h
  armv7m: Explicit error for bad vector table
  armv7m: Replace armv7m.hack with unassigned_access handler
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 29ba0cdc 146871c3

hw/arm/armv7m.c

+0 −8
Original line number Diff line number Diff line
@@ -180,7 +180,6 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, 
    uint64_t entry;

    uint64_t lowaddr;

    int big_endian;

    MemoryRegion *hack = g_new(MemoryRegion, 1);



    if (cpu_model == NULL) {

	cpu_model = "cortex-m3";
@@ -225,13 +224,6 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, 
        }

    }



    /* Hack to map an additional page of ram at the top of the address

       space.  This stops qemu complaining about executing code outside RAM

       when returning from an exception.  */

    memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000, &error_fatal);

    vmstate_register_ram_global(hack);

    memory_region_add_subregion(system_memory, 0xfffff000, hack);



    qemu_register_reset(armv7m_reset, cpu);

    return nvic;

}

hw/block/pflash_cfi01.c

+17 −5
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ struct pflash_t { 
    char *name;

    void *storage;

    VMChangeStateEntry *vmstate;

    bool old_multiple_chip_handling;

};



static int pflash_post_load(void *opaque, int version_id);
@@ -703,7 +704,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) 
    pflash_t *pfl = CFI_PFLASH01(dev);

    uint64_t total_len;

    int ret;

    uint64_t blocks_per_device, device_len;

    uint64_t blocks_per_device, sector_len_per_device, device_len;

    int num_devices;

    Error *local_err = NULL;
@@ -726,8 +727,14 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) 
     * in the cfi_table[].

     */

    num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1;

    if (pfl->old_multiple_chip_handling) {

        blocks_per_device = pfl->nb_blocs / num_devices;

    device_len = pfl->sector_len * blocks_per_device;

        sector_len_per_device = pfl->sector_len;

    } else {

        blocks_per_device = pfl->nb_blocs;

        sector_len_per_device = pfl->sector_len / num_devices;

    }

    device_len = sector_len_per_device * blocks_per_device;



    /* XXX: to be fixed */

#if 0
@@ -832,6 +839,9 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) 
        pfl->cfi_table[0x2A] = 0x0B;

    }

    pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];

    if (!pfl->old_multiple_chip_handling && num_devices > 1) {

        pfl->writeblock_size *= num_devices;

    }



    pfl->cfi_table[0x2B] = 0x00;

    /* Number of erase block regions (uniform) */
@@ -839,8 +849,8 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) 
    /* Erase block region 1 */

    pfl->cfi_table[0x2D] = blocks_per_device - 1;

    pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8;

    pfl->cfi_table[0x2F] = pfl->sector_len >> 8;

    pfl->cfi_table[0x30] = pfl->sector_len >> 16;

    pfl->cfi_table[0x2F] = sector_len_per_device >> 8;

    pfl->cfi_table[0x30] = sector_len_per_device >> 16;



    /* Extended */

    pfl->cfi_table[0x31] = 'P';
@@ -898,6 +908,8 @@ static Property pflash_cfi01_properties[] = { 
    DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),

    DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),

    DEFINE_PROP_STRING("name", struct pflash_t, name),

    DEFINE_PROP_BOOL("old-multiple-chip-handling", struct pflash_t,

                     old_multiple_chip_handling, false),

    DEFINE_PROP_END_OF_LIST(),

};

hw/char/exynos4210_uart.c

+1 −5
Original line number Diff line number Diff line
@@ -306,7 +306,7 @@ static void exynos4210_uart_update_irq(Exynos4210UartState *s) 


static void exynos4210_uart_update_parameters(Exynos4210UartState *s)

{

    int speed, parity, data_bits, stop_bits, frame_size;

    int speed, parity, data_bits, stop_bits;

    QEMUSerialSetParams ssp;

    uint64_t uclk_rate;
@@ -314,9 +314,7 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 
        return;

    }



    frame_size = 1; /* start bit */

    if (s->reg[I_(ULCON)] & 0x20) {

        frame_size++; /* parity bit */

        if (s->reg[I_(ULCON)] & 0x28) {

            parity = 'E';

        } else {
@@ -334,8 +332,6 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 


    data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;



    frame_size += data_bits + stop_bits;



    uclk_rate = 24000000;



    speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +

hw/dma/omap_dma.c

+7 −3
Original line number Diff line number Diff line
@@ -878,15 +878,17 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, 
        ch->burst[0] = (value & 0x0180) >> 7;

        ch->pack[0] = (value & 0x0040) >> 6;

        ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);

        ch->data_type = 1 << (value & 3);

        if (ch->port[0] >= __omap_dma_port_last)

            printf("%s: invalid DMA port %i\n", __FUNCTION__,

                            ch->port[0]);

        if (ch->port[1] >= __omap_dma_port_last)

            printf("%s: invalid DMA port %i\n", __FUNCTION__,

                            ch->port[1]);

        if ((value & 3) == 3)

        ch->data_type = 1 << (value & 3);

        if ((value & 3) == 3) {

            printf("%s: bad data_type for DMA channel\n", __FUNCTION__);

            ch->data_type >>= 1;

        }

        break;



    case 0x02:	/* SYS_DMA_CCR_CH0 */
@@ -1988,8 +1990,10 @@ static void omap_dma4_write(void *opaque, hwaddr addr, 
            fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",

                            __FUNCTION__);

        ch->data_type = 1 << (value & 3);

        if ((value & 3) == 3)

        if ((value & 3) == 3) {

            printf("%s: bad data_type for DMA channel\n", __FUNCTION__);

            ch->data_type >>= 1;

        }

        break;



    case 0x14:	/* DMA4_CEN */

hw/intc/arm_gicv3_cpuif.c

+1 −1
Original line number Diff line number Diff line
@@ -2430,7 +2430,7 @@ static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 
        uint64_t lr = cs->ich_lr_el2[i];



        if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&

            ((lr & ICH_LR_EL2_HW) == 1 || (lr & ICH_LR_EL2_EOI) == 0)) {

            ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) {

            value |= (1 << i);

        }

    }