Commit 3a6606c7 authored by Sai Pavan Boddu's avatar Sai Pavan Boddu Committed by Peter Maydell
Browse files

ssi: xilinx_spips: Skip spi bus update for a few register writes 



A few configuration register writes need not update the spi bus state, so just
return after the register write.

Signed-off-by: default avatarSai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarFrancisco Iglesias <frasse.iglesias@gmail.com>
Tested-by: default avatarFrancisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 6e553f2a

hw/ssi/xilinx_spips.c

+18 −4
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ 
#define R_GPIO              (0x30 / 4)

#define R_LPBK_DLY_ADJ      (0x38 / 4)

#define R_LPBK_DLY_ADJ_RESET (0x33)

#define R_IOU_TAPDLY_BYPASS (0x3C / 4)

#define R_TXD1              (0x80 / 4)

#define R_TXD2              (0x84 / 4)

#define R_TXD3              (0x88 / 4)
@@ -139,6 +140,8 @@ 
#define R_LQSPI_STS         (0xA4 / 4)

#define LQSPI_STS_WR_RECVD      (1 << 1)



#define R_DUMMY_CYCLE_EN    (0xC8 / 4)

#define R_ECO               (0xF8 / 4)

#define R_MOD_ID            (0xFC / 4)



#define R_GQSPI_SELECT          (0x144 / 4)
@@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, 
{

    int mask = ~0;

    XilinxSPIPS *s = opaque;

    bool try_flush = true;



    DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);

    addr >>= 2;
@@ -1019,14 +1023,24 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, 
        tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,

                      s->regs[R_CONFIG] & R_CONFIG_ENDIAN);

        goto no_reg_update;

    /* Skip SPI bus update for below registers writes */

    case R_GPIO:

    case R_LPBK_DLY_ADJ:

    case R_IOU_TAPDLY_BYPASS:

    case R_DUMMY_CYCLE_EN:

    case R_ECO:

        try_flush = false;

        break;

    }

    s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);

no_reg_update:

    if (try_flush) {

        xilinx_spips_update_cs_lines(s);

        xilinx_spips_check_flush(s);

        xilinx_spips_update_cs_lines(s);

        xilinx_spips_update_ixr(s);

    }

}



static const MemoryRegionOps spips_ops = {

    .read = xilinx_spips_read,