Commit 3a5eb5b4 authored by Paolo Bonzini's avatar Paolo Bonzini Committed by Peter Maydell
Browse files

update Linux headers to 4.11 



virtio_mmio.h would be deleted; I am leaving it in though it was a
mistake to add it.

Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent f717e624

include/standard-headers/asm-x86/hyperv.h

+8 −0
Original line number Diff line number Diff line
@@ -73,6 +73,9 @@ 
  */

#define HV_X64_MSR_STAT_PAGES_AVAILABLE		(1 << 8)



/* Crash MSR available */

#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)



/*

 * Feature identification: EBX indicates which flags were specified at

 * partition creation. The format is the same as the partition creation
@@ -144,6 +147,11 @@ 
 */

#define HV_X64_RELAXED_TIMING_RECOMMENDED	(1 << 5)



/*

 * Crash notification flag.

 */

#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)



/* MSR used to identify the guest OS. */

#define HV_X64_MSR_GUEST_OS_ID			0x40000000

include/standard-headers/linux/input-event-codes.h

+1 −1
Original line number Diff line number Diff line
@@ -640,7 +640,7 @@ 
 * Control a data application associated with the currently viewed channel,

 * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)

 */

#define KEY_DATA			0x275

#define KEY_DATA			0x277



#define BTN_TRIGGER_HAPPY		0x2c0

#define BTN_TRIGGER_HAPPY1		0x2c0

include/standard-headers/linux/pci_regs.h

+25 −0
Original line number Diff line number Diff line
@@ -22,6 +22,14 @@ 
#ifndef LINUX_PCI_REGS_H

#define LINUX_PCI_REGS_H



/*

 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of

 * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of

 * configuration space.

 */

#define PCI_CFG_SPACE_SIZE	256

#define PCI_CFG_SPACE_EXP_SIZE	4096



/*

 * Under PCI, each device has 256 bytes of configuration address space,

 * of which the first 64 bytes are standardized as follows:
@@ -674,6 +682,7 @@ 
#define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */

#define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */

#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */

#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */

#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
@@ -965,6 +974,7 @@ 
#define PCI_EXP_DPC_STATUS		8	/* DPC Status */

#define  PCI_EXP_DPC_STATUS_TRIGGER	0x01	/* Trigger Status */

#define  PCI_EXP_DPC_STATUS_INTERRUPT	0x08	/* Interrupt Status */

#define  PCI_EXP_DPC_RP_BUSY		0x10	/* Root Port Busy */



#define PCI_EXP_DPC_SOURCE_ID		10	/* DPC Source Identifier */
@@ -977,4 +987,19 @@ 
#define  PCI_PTM_CTRL_ENABLE		0x00000001  /* PTM enable */

#define  PCI_PTM_CTRL_ROOT		0x00000002  /* Root select */



/* L1 PM Substates */

#define PCI_L1SS_CAP		    4	/* capability register */

#define  PCI_L1SS_CAP_PCIPM_L1_2	 1	/* PCI PM L1.2 Support */

#define  PCI_L1SS_CAP_PCIPM_L1_1	 2	/* PCI PM L1.1 Support */

#define  PCI_L1SS_CAP_ASPM_L1_2		 4	/* ASPM L1.2 Support */

#define  PCI_L1SS_CAP_ASPM_L1_1		 8	/* ASPM L1.1 Support */

#define  PCI_L1SS_CAP_L1_PM_SS		16	/* L1 PM Substates Support */

#define PCI_L1SS_CTL1		    8	/* Control Register 1 */

#define  PCI_L1SS_CTL1_PCIPM_L1_2	1	/* PCI PM L1.2 Enable */

#define  PCI_L1SS_CTL1_PCIPM_L1_1	2	/* PCI PM L1.1 Support */

#define  PCI_L1SS_CTL1_ASPM_L1_2	4	/* ASPM L1.2 Support */

#define  PCI_L1SS_CTL1_ASPM_L1_1	8	/* ASPM L1.1 Support */

#define  PCI_L1SS_CTL1_L1SS_MASK	0x0000000F

#define PCI_L1SS_CTL2		    0xC	/* Control Register 2 */



#endif /* LINUX_PCI_REGS_H */

include/standard-headers/linux/virtio_ids.h

+1 −0
Original line number Diff line number Diff line
@@ -43,4 +43,5 @@ 
#define VIRTIO_ID_INPUT        18 /* virtio input */

#define VIRTIO_ID_VSOCK        19 /* virtio vsock transport */

#define VIRTIO_ID_CRYPTO       20 /* virtio crypto */



#endif /* _LINUX_VIRTIO_IDS_H */

linux-headers/asm-arm/kvm.h

+15 −0
Original line number Diff line number Diff line
@@ -87,9 +87,11 @@ struct kvm_regs { 
/* Supported VGICv3 address types  */

#define KVM_VGIC_V3_ADDR_TYPE_DIST	2

#define KVM_VGIC_V3_ADDR_TYPE_REDIST	3

#define KVM_VGIC_ITS_ADDR_TYPE		4



#define KVM_VGIC_V3_DIST_SIZE		SZ_64K

#define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)

#define KVM_VGIC_V3_ITS_SIZE		(2 * SZ_64K)



#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */

#define KVM_ARM_VCPU_PSCI_0_2		1 /* CPU uses PSCI v0.2 */
@@ -179,10 +181,23 @@ struct kvm_arch_memory_slot { 
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2

#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32

#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)

#define   KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32

#define   KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \

			(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)

#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0

#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)

#define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)

#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3

#define KVM_DEV_ARM_VGIC_GRP_CTRL       4

#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5

#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6

#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO  7

#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT	10

#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \

			(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)

#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff

#define VGIC_LEVEL_INFO_LINE_LEVEL	0



#define   KVM_DEV_ARM_VGIC_CTRL_INIT    0



/* KVM_IRQ_LINE irq field index values */