Commit 39454628 authored by Thiemo Seufer's avatar Thiemo Seufer
Browse files

Simplify mips branch handling. Retire T2 from use. Use TCG for branches. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4320 c046a42c-6fe2-441c-8c8c-71466251a162
parent f730fd27

target-mips/cpu.h

+0 −1
Original line number Diff line number Diff line
@@ -148,7 +148,6 @@ struct CPUMIPSState { 
#if TARGET_LONG_BITS > HOST_LONG_BITS

    target_ulong t0;

    target_ulong t1;

    target_ulong t2;

#endif

    target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC];

    target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC];

target-mips/exec.h

+2 −4
Original line number Diff line number Diff line
@@ -13,11 +13,9 @@ register struct CPUMIPSState *env asm(AREG0); 
#if TARGET_LONG_BITS > HOST_LONG_BITS

#define T0 (env->t0)

#define T1 (env->t1)

#define T2 (env->t2)

#else

register target_ulong T0 asm(AREG1);

register target_ulong T1 asm(AREG2);

register target_ulong T2 asm(AREG3);

register target_ulong T0 asm(AREG2);

register target_ulong T1 asm(AREG3);

#endif



#if defined (USE_HOST_FLOAT_REGS)

target-mips/op.c

+5 −35
Original line number Diff line number Diff line
@@ -247,12 +247,6 @@ 
#include "fop_template.c"

#undef FTN



void op_dup_T0 (void)

{

    T2 = T0;

    FORCE_RET();

}



void op_load_HI (void)

{

    T0 = env->HI[env->current_tc][PARAM1];
@@ -1096,19 +1090,13 @@ OP_COND(ltz, (target_long)T0 < 0); 
/* Branch to register */

void op_save_breg_target (void)

{

    env->btarget = T2;

    FORCE_RET();

}



void op_restore_breg_target (void)

{

    T2 = env->btarget;

    env->btarget = T1;

    FORCE_RET();

}



void op_breg (void)

{

    env->PC[env->current_tc] = T2;

    env->PC[env->current_tc] = env->btarget;

    FORCE_RET();

}
@@ -1129,25 +1117,13 @@ void op_save_btarget64 (void) 
/* Conditional branch */

void op_set_bcond (void)

{

    T2 = T0;

    FORCE_RET();

}



void op_save_bcond (void)

{

    env->bcond = T2;

    FORCE_RET();

}



void op_restore_bcond (void)

{

    T2 = env->bcond;

    env->bcond = T0;

    FORCE_RET();

}



void op_jnz_T2 (void)

void op_jnz_bcond (void)

{

    if (T2)

    if (env->bcond)

        GOTO_LABEL_PARAM(1);

    FORCE_RET();

}
@@ -3116,12 +3092,6 @@ void op_debug (void) 
    FORCE_RET();

}



void op_set_lladdr (void)

{

    env->CP0_LLAddr = T2;

    FORCE_RET();

}



void debug_pre_eret (void);

void debug_post_eret (void);

void op_eret (void)

target-mips/op_template.c

+0 −8
Original line number Diff line number Diff line
@@ -43,12 +43,6 @@ void glue(op_store_T1_gpr_gpr, REG) (void) 
    FORCE_RET();

}



void glue(op_load_gpr_T2_gpr, REG) (void)

{

    T2 = env->gpr[env->current_tc][REG];

    FORCE_RET();

}





void glue(op_load_srsgpr_T0_gpr, REG) (void)

{
@@ -78,7 +72,6 @@ void glue(op_store_T0_srsgpr_gpr, REG) (void) 


SET_RESET(T0, _T0)

SET_RESET(T1, _T1)

SET_RESET(T2, _T2)



#undef SET_RESET
@@ -92,7 +85,6 @@ SET_RESET(T2, _T2) 


SET64(T0, _T0)

SET64(T1, _T1)

SET64(T2, _T2)



#undef SET64

target-mips/translate.c

+48 −29
Original line number Diff line number Diff line
@@ -421,6 +421,8 @@ enum { 
    OPC_NMSUB_PS= 0x3E | OPC_CP3,

};



/* global register indices */

static TCGv cpu_env, current_tc_regs, cpu_T[2];



const unsigned char *regnames[] =

    { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
@@ -448,7 +450,6 @@ static always_inline void func(int n) \ 
/* General purpose registers moves */

GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);

GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);

GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);



GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);

GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
@@ -599,15 +600,6 @@ do { \ 
    }                                                                         \

} while (0)



#define GEN_LOAD_REG_T2(Rn)                                                   \

do {                                                                          \

    if (Rn == 0) {                                                            \

        gen_op_reset_T2();                                                    \

    } else {                                                                  \

        gen_op_load_gpr_T2(Rn);                                               \

    }                                                                         \

} while (0)



#define GEN_LOAD_SRSREG_TN(Tn, Rn)                                            \

do {                                                                          \

    if (Rn == 0) {                                                            \
@@ -714,14 +706,9 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc) 
        ctx->saved_hflags = ctx->hflags;

        switch (ctx->hflags & MIPS_HFLAG_BMASK) {

        case MIPS_HFLAG_BR:

            gen_op_save_breg_target();

            break;

        case MIPS_HFLAG_BC:

            gen_op_save_bcond();

            /* fall through */

        case MIPS_HFLAG_BL:

            /* bcond was already saved by the BL insn */

            /* fall through */

        case MIPS_HFLAG_B:

            gen_save_btarget(ctx->btarget);

            break;
@@ -734,15 +721,11 @@ static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx) 
    ctx->saved_hflags = ctx->hflags;

    switch (ctx->hflags & MIPS_HFLAG_BMASK) {

    case MIPS_HFLAG_BR:

        gen_op_restore_breg_target();

        break;

    case MIPS_HFLAG_B:

        ctx->btarget = env->btarget;

        break;

    case MIPS_HFLAG_BC:

    case MIPS_HFLAG_BL:

    case MIPS_HFLAG_B:

        ctx->btarget = env->btarget;

        gen_op_restore_bcond();

        break;

    }

}
@@ -1770,6 +1753,19 @@ static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong des 
    }

}



static inline void tcg_gen_set_bcond(void)

{

    tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));

}



static inline void tcg_gen_jnz_bcond(int label)

{

    int r_tmp = tcg_temp_new(TCG_TYPE_TL);



    tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));

    tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_i32(0), label);

}



/* Branches (before delay slot) */

static void gen_compute_branch (DisasContext *ctx, uint32_t opc,

                                int rs, int rt, int32_t offset)
@@ -1838,7 +1834,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, 
            generate_exception(ctx, EXCP_RI);

            return;

        }

        GEN_LOAD_REG_T2(rs);

        GEN_LOAD_REG_T1(rs);

        gen_op_save_breg_target();

        break;

    default:

        MIPS_INVAL("branch/jump");
@@ -1983,7 +1980,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, 
            MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);

        not_likely:

            ctx->hflags |= MIPS_HFLAG_BC;

            gen_op_set_bcond();

            tcg_gen_set_bcond();

            break;

        case OPC_BLTZALL:

            gen_op_ltz();
@@ -1991,8 +1988,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, 
            MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);

        likely:

            ctx->hflags |= MIPS_HFLAG_BL;

            gen_op_set_bcond();

            gen_op_save_bcond();

            tcg_gen_set_bcond();

            break;

        default:

            MIPS_INVAL("conditional branch/jump");
@@ -4863,8 +4859,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, 
        opn = "bc1tl";

    likely:

        ctx->hflags |= MIPS_HFLAG_BL;

        gen_op_set_bcond();

        gen_op_save_bcond();

        tcg_gen_set_bcond();

        break;

    case OPC_BC1FANY2:

        gen_op_bc1any2f(cc);
@@ -4883,7 +4878,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, 
        opn = "bc1any4t";

    not_likely:

        ctx->hflags |= MIPS_HFLAG_BC;

        gen_op_set_bcond();

        tcg_gen_set_bcond();

        break;

    default:

        MIPS_INVAL(opn);
@@ -6056,7 +6051,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) 
        /* Handle blikely not taken case */

        MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);

        l1 = gen_new_label();

        gen_op_jnz_T2(l1);

        tcg_gen_jnz_bcond(l1);

        gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);

        gen_goto_tb(ctx, 1, ctx->pc + 4);

        gen_set_label(l1);
@@ -6612,7 +6607,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) 
            {

              int l1;

              l1 = gen_new_label();

              gen_op_jnz_T2(l1);

              tcg_gen_jnz_bcond(l1);

              gen_goto_tb(ctx, 1, ctx->pc + 4);

              gen_set_label(l1);

              gen_goto_tb(ctx, 0, ctx->btarget);
@@ -6877,6 +6872,29 @@ void cpu_dump_state (CPUState *env, FILE *f, 
#endif

}



static void mips_tcg_init(void)

{

    static int inited;



    /* Initialize various static tables. */

    if (inited)

	return;



    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");

    current_tc_regs = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG1, "current_tc_regs");

#if TARGET_LONG_BITS > HOST_LONG_BITS

    cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,

                                  TCG_AREG0, offsetof(CPUState, t0), "T0");

    cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,

                                  TCG_AREG0, offsetof(CPUState, t1), "T1");

#else

    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T0");

    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T1");

#endif



    inited = 1;

}



#include "translate_init.c"



CPUMIPSState *cpu_mips_init (const char *cpu_model)
@@ -6894,6 +6912,7 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model) 


    cpu_exec_init(env);

    env->cpu_model_str = cpu_model;

    mips_tcg_init();

    cpu_reset(env);

    return env;

}