Commit 3944d58d authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Assert immh != 0 in disas_simd_shift_imm 



Coverity raised a shed-load of errors cascading from inferring
that clz32(immh) might yield 32, from immh might be 0.

While immh cannot be 0 from encoding, it is not obvious even to
a human how we've checked that: via the filtering provided by
data_proc_simd[].

Reported-by: Coverity (CID 1421923, and more)
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200320160622.8040-3-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ae1111d4

target/arm/translate-a64.c

+3 −0
Original line number Diff line number Diff line
@@ -10405,6 +10405,9 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) 
    bool is_u = extract32(insn, 29, 1);

    bool is_q = extract32(insn, 30, 1);



    /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */

    assert(immh != 0);



    switch (opcode) {

    case 0x08: /* SRI */

        if (!is_u) {