Commit 379d83f2 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-29-2019' into staging 



MIPS queue for August 29th, 2019

# gpg: Signature made Thu 29 Aug 2019 11:19:28 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-aug-29-2019: (31 commits)
  target/mips: Fix emulation of ST.W in system mode
  target/mips: Clean up handling of CP0 register 31
  target/mips: Clean up handling of CP0 register 30
  target/mips: Clean up handling of CP0 register 29
  target/mips: Clean up handling of CP0 register 28
  target/mips: Clean up handling of CP0 register 27
  target/mips: Clean up handling of CP0 register 26
  target/mips: Clean up handling of CP0 register 25
  target/mips: Clean up handling of CP0 register 24
  target/mips: Clean up handling of CP0 register 23
  target/mips: Clean up handling of CP0 register 20
  target/mips: Clean up handling of CP0 register 19
  target/mips: Clean up handling of CP0 register 18
  target/mips: Clean up handling of CP0 register 17
  target/mips: Clean up handling of CP0 register 16
  target/mips: Clean up handling of CP0 register 15
  target/mips: Clean up handling of CP0 register 14
  target/mips: Clean up handling of CP0 register 13
  target/mips: Clean up handling of CP0 register 12
  target/mips: Clean up handling of CP0 register 11
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 03a61905 abd4393d

target/mips/cpu.h

+90 −23
Original line number Diff line number Diff line
@@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t; 
 *     Register 16       Register 17       Register 18       Register 19

 *     -----------       -----------       -----------       -----------

 *

 * 0   Config            LLAddr            WatchLo           WatchHi

 * 1   Config1           MAAR              WatchLo           WatchHi

 * 2   Config2           MAARI             WatchLo           WatchHi

 * 3   Config3                             WatchLo           WatchHi

 * 4   Config4                             WatchLo           WatchHi

 * 5   Config5                             WatchLo           WatchHi

 * 6                                       WatchLo           WatchHi

 * 7                                       WatchLo           WatchHi

 * 0   Config            LLAddr            WatchLo0          WatchHi

 * 1   Config1           MAAR              WatchLo1          WatchHi

 * 2   Config2           MAARI             WatchLo2          WatchHi

 * 3   Config3                             WatchLo3          WatchHi

 * 4   Config4                             WatchLo4          WatchHi

 * 5   Config5                             WatchLo5          WatchHi

 * 6                                       WatchLo6          WatchHi

 * 7                                       WatchLo7          WatchHi

 *

 *

 *     Register 20       Register 21       Register 22       Register 23
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t; 
 *

 * 0   DataLo            DataHi            ErrorEPC          DESAVE

 * 1   TagLo             TagHi

 * 2   DataLo            DataHi                              KScratch<n>

 * 3   TagLo             TagHi                               KScratch<n>

 * 4   DataLo            DataHi                              KScratch<n>

 * 5   TagLo             TagHi                               KScratch<n>

 * 6   DataLo            DataHi                              KScratch<n>

 * 7   TagLo             TagHi                               KScratch<n>

 * 2   DataLo1           DataHi1                             KScratch<n>

 * 3   TagLo1            TagHi1                              KScratch<n>

 * 4   DataLo2           DataHi2                             KScratch<n>

 * 5   TagLo2            TagHi2                              KScratch<n>

 * 6   DataLo3           DataHi3                             KScratch<n>

 * 7   TagLo3            TagHi3                              KScratch<n>

 *

 */

#define CP0_REGISTER_00     0
@@ -277,29 +277,63 @@ typedef struct mips_def_t mips_def_t; 


/* CP0 Register 00 */

#define CP0_REG00__INDEX           0

#define CP0_REG00__MVPCONTROL      1

#define CP0_REG00__MVPCONF0        2

#define CP0_REG00__MVPCONF1        3

#define CP0_REG00__VPCONTROL       4

/* CP0 Register 01 */

#define CP0_REG01__RANDOM          0

#define CP0_REG01__VPECONTROL      1

#define CP0_REG01__VPECONF0        2

#define CP0_REG01__VPECONF1        3

#define CP0_REG01__YQMASK          4

#define CP0_REG01__VPESCHEDULE     5

#define CP0_REG01__VPESCHEFBACK    6

#define CP0_REG01__VPEOPT          7

/* CP0 Register 02 */

#define CP0_REG02__ENTRYLO0        0

#define CP0_REG02__TCSTATUS        1

#define CP0_REG02__TCBIND          2

#define CP0_REG02__TCRESTART       3

#define CP0_REG02__TCHALT          4

#define CP0_REG02__TCCONTEXT       5

#define CP0_REG02__TCSCHEDULE      6

#define CP0_REG02__TCSCHEFBACK     7

/* CP0 Register 03 */

#define CP0_REG03__ENTRYLO1        0

#define CP0_REG03__GLOBALNUM       1

#define CP0_REG03__TCOPT           7

/* CP0 Register 04 */

#define CP0_REG04__CONTEXT         0

#define CP0_REG04__CONTEXTCONFIG   1

#define CP0_REG04__USERLOCAL       2

#define CP0_REG04__XCONTEXTCONFIG  3

#define CP0_REG04__DBGCONTEXTID    4

#define CP0_REG00__MMID            5

/* CP0 Register 05 */

#define CP0_REG05__PAGEMASK        0

#define CP0_REG05__PAGEGRAIN       1

#define CP0_REG05__SEGCTL0         2

#define CP0_REG05__SEGCTL1         3

#define CP0_REG05__SEGCTL2         4

#define CP0_REG05__PWBASE          5

#define CP0_REG05__PWFIELD         6

#define CP0_REG05__PWSIZE          7

/* CP0 Register 06 */

#define CP0_REG06__WIRED           0

#define CP0_REG06__SRSCONF0        1

#define CP0_REG06__SRSCONF1        2

#define CP0_REG06__SRSCONF2        3

#define CP0_REG06__SRSCONF3        4

#define CP0_REG06__SRSCONF4        5

#define CP0_REG06__PWCTL           6

/* CP0 Register 07 */

#define CP0_REG07__HWRENA          0

/* CP0 Register 08 */

#define CP0_REG08__BADVADDR        0

#define CP0_REG08__BADINSTR        1

#define CP0_REG08__BADINSTRP       2

#define CP0_REG08__BADINSTRX       3

/* CP0 Register 09 */

#define CP0_REG09__COUNT           0

#define CP0_REG09__SAARI           6
@@ -308,6 +342,7 @@ typedef struct mips_def_t mips_def_t; 
#define CP0_REG10__ENTRYHI         0

#define CP0_REG10__GUESTCTL1       4

#define CP0_REG10__GUESTCTL2       5

#define CP0_REG10__GUESTCTL3       6

/* CP0 Register 11 */

#define CP0_REG11__COMPARE         0

#define CP0_REG11__GUESTCTL0EXT    4
@@ -315,17 +350,24 @@ typedef struct mips_def_t mips_def_t; 
#define CP0_REG12__STATUS          0

#define CP0_REG12__INTCTL          1

#define CP0_REG12__SRSCTL          2

#define CP0_REG12__SRSMAP          3

#define CP0_REG12__VIEW_IPL        4

#define CP0_REG12__SRSMAP2         5

#define CP0_REG12__GUESTCTL0       6

#define CP0_REG12__GTOFFSET        7

/* CP0 Register 13 */

#define CP0_REG13__CAUSE           0

#define CP0_REG13__VIEW_RIPL       4

#define CP0_REG13__NESTEDEXC       5

/* CP0 Register 14 */

#define CP0_REG14__EPC             0

#define CP0_REG14__NESTEDEPC       2

/* CP0 Register 15 */

#define CP0_REG15__PRID            0

#define CP0_REG15__EBASE           1

#define CP0_REG15__CDMMBASE        2

#define CP0_REG15__CMGCRBASE       3

#define CP0_REG15__BEVVA           4

/* CP0 Register 16 */

#define CP0_REG16__CONFIG          0

#define CP0_REG16__CONFIG1         1
@@ -333,7 +375,8 @@ typedef struct mips_def_t mips_def_t; 
#define CP0_REG16__CONFIG3         3

#define CP0_REG16__CONFIG4         4

#define CP0_REG16__CONFIG5         5

#define CP0_REG00__CONFIG7         7

#define CP0_REG16__CONFIG6         6

#define CP0_REG16__CONFIG7         7

/* CP0 Register 17 */

#define CP0_REG17__LLADDR          0

#define CP0_REG17__MAAR            1
@@ -343,17 +386,31 @@ typedef struct mips_def_t mips_def_t; 
#define CP0_REG18__WATCHLO1        1

#define CP0_REG18__WATCHLO2        2

#define CP0_REG18__WATCHLO3        3

#define CP0_REG18__WATCHLO4        4

#define CP0_REG18__WATCHLO5        5

#define CP0_REG18__WATCHLO6        6

#define CP0_REG18__WATCHLO7        7

/* CP0 Register 19 */

#define CP0_REG19__WATCHHI0        0

#define CP0_REG19__WATCHHI1        1

#define CP0_REG19__WATCHHI2        2

#define CP0_REG19__WATCHHI3        3

#define CP0_REG19__WATCHHI4        4

#define CP0_REG19__WATCHHI5        5

#define CP0_REG19__WATCHHI6        6

#define CP0_REG19__WATCHHI7        7

/* CP0 Register 20 */

#define CP0_REG20__XCONTEXT        0

/* CP0 Register 21 */

/* CP0 Register 22 */

/* CP0 Register 23 */

#define CP0_REG23__DEBUG           0

#define CP0_REG23__TRACECONTROL    1

#define CP0_REG23__TRACECONTROL2   2

#define CP0_REG23__USERTRACEDATA1  3

#define CP0_REG23__TRACEIBPC       4

#define CP0_REG23__TRACEDBPC       5

#define CP0_REG23__DEBUG2          6

/* CP0 Register 24 */

#define CP0_REG24__DEPC            0

/* CP0 Register 25 */
@@ -366,17 +423,27 @@ typedef struct mips_def_t mips_def_t; 
#define CP0_REG25__PERFCTL3        6

#define CP0_REG25__PERFCNT3        7

/* CP0 Register 26 */

#define CP0_REG00__ERRCTL          0

#define CP0_REG26__ERRCTL          0

/* CP0 Register 27 */

#define CP0_REG27__CACHERR         0

/* CP0 Register 28 */

#define CP0_REG28__ITAGLO          0

#define CP0_REG28__IDATALO         1

#define CP0_REG28__DTAGLO          2

#define CP0_REG28__DDATALO         3

#define CP0_REG28__TAGLO           0

#define CP0_REG28__DATALO          1

#define CP0_REG28__TAGLO1          2

#define CP0_REG28__DATALO1         3

#define CP0_REG28__TAGLO2          4

#define CP0_REG28__DATALO2         5

#define CP0_REG28__TAGLO3          6

#define CP0_REG28__DATALO3         7

/* CP0 Register 29 */

#define CP0_REG29__IDATAHI         1

#define CP0_REG29__DDATAHI         3

#define CP0_REG29__TAGHI           0

#define CP0_REG29__DATAHI          1

#define CP0_REG29__TAGHI1          2

#define CP0_REG29__DATAHI1         3

#define CP0_REG29__TAGHI2          4

#define CP0_REG29__DATAHI2         5

#define CP0_REG29__TAGHI3          6

#define CP0_REG29__DATAHI3         7

/* CP0 Register 30 */

#define CP0_REG30__ERROREPC        0

/* CP0 Register 31 */
@@ -546,7 +613,6 @@ struct CPUMIPSState { 
 * CP0 Register 4

 */

    target_ulong CP0_Context;

    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];

    int32_t CP0_MemoryMapID;

/*

 * CP0 Register 5
@@ -957,6 +1023,7 @@ struct CPUMIPSState { 
 * CP0 Register 31

 */

    int32_t CP0_DESAVE;

    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];



    /* We waste some space so we can handle shadow registers like TCs. */

    TCState tcs[MIPS_SHADOW_SET_MAX];

target/mips/op_helper.c

+8 −8
Original line number Diff line number Diff line
@@ -4692,15 +4692,15 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, 
    ensure_writable_pages(env, addr, mmu_idx, GETPC());

#if !defined(CONFIG_USER_ONLY)

#if !defined(HOST_WORDS_BIGENDIAN)

    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);

    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);

    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);

    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);

    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());

    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());

    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());

    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());

#else

    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);

    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);

    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);

    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);

    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());

    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());

    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());

    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());

#endif

#else

#if !defined(HOST_WORDS_BIGENDIAN)

target/mips/translate.c

+587 −555

File changed.

Preview size limit exceeded, changes collapsed.