Commit 3774030a authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Add generic vector ops for multiplication 



Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 212be173

accel/tcg/tcg-runtime-gvec.c

+44 −0
Original line number Diff line number Diff line
@@ -166,6 +166,50 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) 
    clear_high(d, oprsz, desc);

}



void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc)

{

    intptr_t oprsz = simd_oprsz(desc);

    intptr_t i;



    for (i = 0; i < oprsz; i += sizeof(vec8)) {

        *(vec8 *)(d + i) = *(vec8 *)(a + i) * *(vec8 *)(b + i);

    }

    clear_high(d, oprsz, desc);

}



void HELPER(gvec_mul16)(void *d, void *a, void *b, uint32_t desc)

{

    intptr_t oprsz = simd_oprsz(desc);

    intptr_t i;



    for (i = 0; i < oprsz; i += sizeof(vec16)) {

        *(vec16 *)(d + i) = *(vec16 *)(a + i) * *(vec16 *)(b + i);

    }

    clear_high(d, oprsz, desc);

}



void HELPER(gvec_mul32)(void *d, void *a, void *b, uint32_t desc)

{

    intptr_t oprsz = simd_oprsz(desc);

    intptr_t i;



    for (i = 0; i < oprsz; i += sizeof(vec32)) {

        *(vec32 *)(d + i) = *(vec32 *)(a + i) * *(vec32 *)(b + i);

    }

    clear_high(d, oprsz, desc);

}



void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)

{

    intptr_t oprsz = simd_oprsz(desc);

    intptr_t i;



    for (i = 0; i < oprsz; i += sizeof(vec64)) {

        *(vec64 *)(d + i) = *(vec64 *)(a + i) * *(vec64 *)(b + i);

    }

    clear_high(d, oprsz, desc);

}



void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)

{

    intptr_t oprsz = simd_oprsz(desc);

accel/tcg/tcg-runtime.h

+5 −0
Original line number Diff line number Diff line
@@ -152,6 +152,11 @@ DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) 
DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_4(gvec_mul8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

tcg/README

+4 −0
Original line number Diff line number Diff line
@@ -538,6 +538,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. 


  Similarly, v0 = v1 - v2.



* mul_vec   v0, v1, v2



  Similarly, v0 = v1 * v2.



* neg_vec   v0, v1



  Similarly, v0 = -v1.

tcg/tcg-op-gvec.c

+29 −0
Original line number Diff line number Diff line
@@ -1280,6 +1280,35 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, 
    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);

}



void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,

                      uint32_t bofs, uint32_t oprsz, uint32_t maxsz)

{

    static const GVecGen3 g[4] = {

        { .fniv = tcg_gen_mul_vec,

          .fno = gen_helper_gvec_mul8,

          .opc = INDEX_op_mul_vec,

          .vece = MO_8 },

        { .fniv = tcg_gen_mul_vec,

          .fno = gen_helper_gvec_mul16,

          .opc = INDEX_op_mul_vec,

          .vece = MO_16 },

        { .fni4 = tcg_gen_mul_i32,

          .fniv = tcg_gen_mul_vec,

          .fno = gen_helper_gvec_mul32,

          .opc = INDEX_op_mul_vec,

          .vece = MO_32 },

        { .fni8 = tcg_gen_mul_i64,

          .fniv = tcg_gen_mul_vec,

          .fno = gen_helper_gvec_mul64,

          .opc = INDEX_op_mul_vec,

          .prefer_i64 = TCG_TARGET_REG_BITS == 64,

          .vece = MO_64 },

    };



    tcg_debug_assert(vece <= MO_64);

    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);

}



/* Perform a vector negation using normal negation and a mask.

   Compare gen_subv_mask above.  */

static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)

tcg/tcg-op-gvec.h

+2 −0
Original line number Diff line number Diff line
@@ -176,6 +176,8 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, 
                      uint32_t bofs, uint32_t oprsz, uint32_t maxsz);

void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,

                      uint32_t bofs, uint32_t oprsz, uint32_t maxsz);

void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,

                      uint32_t bofs, uint32_t oprsz, uint32_t maxsz);



void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,

                      uint32_t bofs, uint32_t oprsz, uint32_t maxsz);